Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 55 - diyAudio
Go Back   Home > Forums > Source & Line > Digital Line Level

Digital Line Level DACs, Digital Crossovers, Equalizers, etc.

Please consider donating to help us continue to serve you.

Ads on/off / Custom Title / More PMs / More album space / Advanced printing & mass image saving
Reply
 
Thread Tools Search this Thread
Old 17th May 2012, 12:53 AM   #541
qusp is offline qusp  Australia
diyAudio Member
 
qusp's Avatar
 
Join Date: Oct 2009
Location: Brisbane, Australia
hehe expert, the people here I call experts put me to shame! but yes do that first and allow room for shunt or battery for the clock board. powering the clock board or clocks and flip flops directly with upgraded power may be more worthwhile, wont create as much heat and wont require such significant heatsinking. try powering the whole thing with linear or battery first and then upgrade the clock board supplies as an upgrade, if you dont hear the difference of that, then I dont believe you will hear it for powering the whole thing. also consider Demians regulator design

Last edited by qusp; 17th May 2012 at 12:56 AM.
  Reply With Quote
Old 18th May 2012, 12:07 AM   #542
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Default Successfully running ESS9018 (Buffalo III) at synchronized mode

I hooked up the FIFO KIT and B III into synchronized configuration yesterday. It runs great without any problem. The setup is easier than I thought. Please see the attached pictures for details(find the names for the meaning of the pictures).

Step1: Remove the CCHD950 OEM 100Mhz local oscillator
After the CCHD950 was removed, I found TP has already left a backdoor for the sync mode. There is a 3 pin socket underneath, GND, VDDXO and CLOCK
Tips: protect the surrounding component with thermal tape and heat the back of the PCB first to avoid any possible damage.

Step2: Assemble a U.FL socket
I still think U.FL socket is better for the clock signals, so I just soldered it on the BIII board. Signal (MCLK input) to CLOCK and shield to GND. However, using the 3 pin dip connector will make it easier switching between sync and async mode, so later on, maybe I have to give up the U.FL socket and switch back to 3 pin dip connector.

Step3: set up the Dual XO Clock board into double speed mode with 45.1584 MHz and 49.1520 MHz oscillators.
Please see the attached PDF guidance for details. Please be notice, jumpers have to be set exactly as what directed in the doc. Actually I finished this document 6 weeks ago, but I have to confirm it by myself before I public it.

Step4: connecting the cables
I2S output to I2S input, MCLK output to MCLK input.

Step5: Enjoy the music.

It runs right away without any hesitating. The LOCK LED keeps lighting all the way indicating it synchronized with the input I2S stream unconditional even I set the bandwidth switches to 'lowest' and run music at 192KHz from an USB.

According to my understanding on the ESS9018 sync mode:

1, The DAC is running by the MCLK directly no matter what mode it is, sync or async, DPLL is only used for re-sampling job according to the ASRC algorithm , it doesn't generate any real clock;

2, In the async mode, DPLL re-samples the input I2S asynchronizely, the bandwidth of the DPLL could not go infinite to lock with input I2S due to the phase difference between clocks. With the limited bandwidth, all jitter below will be path through and converted into re-sampling jitter and all above will be removed and determined by the MCLK.

3, In the sync mode, DPLL locks to input I2S un-conditionally with infinite (even better than the 'lowest') bandwidth because the I2S is generated by same MCLK with fixed relationship of 256*,512*,1024* and so on. In this case, the DAC jitter is 100% determined by MCLK itself, so the finial sound will be highly depend on the FIFO clock.

In my configuration, ESS9018 sounds great in both of the modes, sync and async. I even couldn't tell which one is better. But there is slightly difference on the sound style. Async is more like ESS9018 J while sync is more like classical high-end DACs. I usually don't talk much about the sound, because too many psychological factors and personal feelings mixed. I'll left this part to others, trust your ears and try to find out the best parameter settings of 9018 for the sync mode.

90.3168MHz and 98.3040MHz would be more optimized frequency for ESS9018, but it’s very hard to find out the really nice XOs with those frequencies so far, except the si570 based real time programmable low jitter XO I could think about.

I added an additional piece of heat sink and make it facing up. The stable working temp on the surface reduced from 60C to 53C J.

Have a nice weekend.

Ian
Attached Images
File Type: jpg RemoveCCHD950.JPG (738.8 KB, 752 views)
File Type: jpg AssembleU.FL.JPG (524.1 KB, 649 views)
File Type: jpg DoubleSpeedClocks.JPG (583.8 KB, 625 views)
File Type: jpg BIIIinSyncMode.JPG (522.0 KB, 601 views)
File Type: jpg SyncModeHookup.JPG (547.6 KB, 591 views)
File Type: jpg AddSomeHeatsink.JPG (480.8 KB, 345 views)
File Type: jpg LockAtLowestBandwidth.JPG (638.0 KB, 347 views)
Attached Files
File Type: zip DuobleSpeedModeDualXOclockBoard.zip (69.5 KB, 123 views)
__________________
Ian GBV - I2S to PCM converter board & FIFO KIT
http://www.diyaudio.com/forums/group...ml#post3662743

Last edited by iancanada; 18th May 2012 at 12:22 AM.
  Reply With Quote
Old 18th May 2012, 01:55 AM   #543
qusp is offline qusp  Australia
diyAudio Member
 
qusp's Avatar
 
Join Date: Oct 2009
Location: Brisbane, Australia
good job! yeah no magic to sync mode, you just need the right clock/i2s source.

guess i'll still be sending it back for quad mode setting

i've been meaning to ask mate, where do you get this spiral cable-wrap stuff? i've not seen it before your builds and it seems very handy
  Reply With Quote
Old 18th May 2012, 02:00 AM   #544
diyAudio Member
 
Join Date: Feb 2009
Location: Brisbane, Australia
Great post Ian! Especially the pics showing the area of interest on the BIII very clearly, sometimes quite hard to get those tiny areas in focus properly.

Quote:
Originally Posted by qusp View Post
i've been meaning to ask mate, where do you get this spiral cable-wrap stuff? i've not seen it before your builds and it seems very handy
It seems like a miniaturised version of - Zone Hardware Large Cord Wrap 2m at $11.96 in Cable Organisers

I'm not sure where you get them to suit smaller cables I've only seen it on bundles of larger cables rather than individual wires that look like they're closer to 24awg.
  Reply With Quote
Old 18th May 2012, 02:18 AM   #545
diyAudio Member
 
Join Date: Feb 2009
Location: Brisbane, Australia
Just thought that I would add this link in here for anyone wanting to use FIFO dual XO as external master clock to BIII.

On the twisted pear forums Brian suggests simply removing power to the onboard clock and connecting to the pin headers from underside of the BIII and leaving the onboard 100MHz CCHD950 in place unpowered.

Do you have any thoughts on that Ian?
  Reply With Quote
Old 18th May 2012, 02:28 AM   #546
qusp is offline qusp  Australia
diyAudio Member
 
qusp's Avatar
 
Join Date: Oct 2009
Location: Brisbane, Australia
yeah thats belden networking cable 1583A if i'm not mistaken and it is indeed 24awg solid copper internally

heres some

but I shudder to think of the shipping fee, these places usualy ream you. found something similar here in AU but its not as useful. the one you linked is no good. the ones above go down to internal diameter of 1/8" up to 3" but the 1/4 or 3/8 seems perfect.

Ian is already aware of that clock business, I also mentioned it on the previous page or before. it will work and thats what i'm doing at the moment, but the crystek doesnt have a shutdown mode, so leaving it unpowered means whatever is hanging off the end of the clock circuit in its 'HiZ mode' internally is in parallel with the input clock. also wiuth the clock there there isnt really anywhere convenient on the b3 to connect anything but bare wire unlike on the ackodac and buff II

Last edited by qusp; 18th May 2012 at 02:32 AM.
  Reply With Quote
Old 18th May 2012, 02:30 AM   #547
glt is offline glt  United States
diyAudio Member
 
Join Date: Oct 2004
Quote:
Originally Posted by iancanada View Post
...
90.3168MHz and 98.3040MHz would be more optimized frequency for ESS9018, but itís very hard to find out the really nice XOs with those frequencies so far, except the si570 based real time programmable low jitter XO I could think about.

...Ian
Seem a frequency of 40Mhz is optimized for the DAC: ESS Sabre Reference DAC (8-channel)

In addition, try turning oversampling On/Off...
__________________
www.hifiduino.wordpress.com
  Reply With Quote
Old 18th May 2012, 02:38 AM   #548
diyAudio Member
 
iancanada's Avatar
 
Join Date: Dec 2009
Location: Toronto
Quote:
Originally Posted by hochopeper View Post
Just thought that I would add this link in here for anyone wanting to use FIFO dual XO as external master clock to BIII.

On the twisted pear forums Brian suggests simply removing power to the onboard clock and connecting to the pin headers from underside of the BIII and leaving the onboard 100MHz CCHD950 in place unpowered.

Do you have any thoughts on that Ian?
How about an IC output pin without power up? If there is ESD protecting diode.... the new clock signal will be suffer....and consider the empty pin as a capacitive load .... for a RF signal like a clock....also no good. Yes, my point is... you have to remove it .
__________________
Ian GBV - I2S to PCM converter board & FIFO KIT
http://www.diyaudio.com/forums/group...ml#post3662743
  Reply With Quote
Old 18th May 2012, 02:52 AM   #549
diyAudio Member
 
Join Date: Feb 2009
Location: Brisbane, Australia
Quote:
Originally Posted by qusp View Post
Ian is already aware of that clock business, I also mentioned it on the previous page or before. it will work and thats what i'm doing at the moment, but the crystek doesnt have a shutdown mode, so leaving it unpowered means whatever is hanging off the end of the clock circuit in its 'HiZ mode' internally is in parallel with the input clock. also wiuth the clock there there isnt really anywhere convenient on the b3 to connect anything but bare wire unlike on the ackodac and buff II
Now you mention that I remember that post you mention, I didn't see the significance at the time since I hadn't looked at the BIII layout other than the main photo on the TPA site which really didn't show the juicy details.

Quote:
Originally Posted by iancanada View Post
How about an IC output pin without power up? If there is ESD protecting diode.... the new clock signal will be suffer....and consider the empty pin as a capacitive load .... for a RF signal like a clock....also no good. Yes, my point is... you have to remove it .
When you put it that way ...

It seems like some may be better off convincing TPA to ship the BIII with the CCHD950 not mounted at all.
  Reply With Quote
Old 18th May 2012, 03:01 AM   #550
qusp is offline qusp  Australia
diyAudio Member
 
qusp's Avatar
 
Join Date: Oct 2009
Location: Brisbane, Australia
Quote:
Originally Posted by glt View Post
Seem a frequency of 40Mhz is optimized for the DAC: ESS Sabre Reference DAC (8-channel)

In addition, try turning oversampling On/Off...
he didnt say that, yes the demo board comes with 40Mhz but the dac was specified to run MAX 192 and async mode. the maybe yes, maybe not 1db loss he mentions will only be because of increased thermal, voltage and current noiseI would think. seems its a bit of a different sitruation we are now in, using the dac beyond its initial spec in sync mode with 384+ sources that didnt exists at the time of the dacs inception

Quote:
Originally Posted by iancanada View Post
How about an IC output pin without power up? If there is ESD protecting diode.... the new clock signal will be suffer....and consider the empty pin as a capacitive load .... for a RF signal like a clock....also no good. Yes, my point is... you have to remove it .
yup, i'll be removing mine once the testing phase is over ; I probably should have actually just sent my dac boards down to acko when I sent the MCUs for update given I cant use them while they are gone anyway. but while testing different stuff out its handy to be able to use either mode and connect sources without HAVING to have the fifo inline, particularly while its still not updated to accept higher speeds

Last edited by qusp; 18th May 2012 at 03:04 AM.
  Reply With Quote

Reply


Hide this!Advertise here!
Thread Tools Search this Thread
Search this Thread:

Advanced Search

Posting Rules
You may not post new threads
You may not post replies
You may not post attachments
You may not edit your posts

BB code is On
Smilies are On
[IMG] code is On
HTML code is Off
Trackbacks are Off
Pingbacks are Off
Refbacks are Off


Similar Threads
Thread Thread Starter Forum Replies Last Post
XMOS-based Asynchronous USB to I2S interface Lorien Digital Source 2160 Yesterday 01:09 AM
exaU2I - Multi-Channel Asynchronous USB to I2S Interface exa065 exaDevices 1357 3rd March 2014 08:51 PM
DAC chip selection + I2S jitter questions drwho9437 Digital Line Level 2 26th July 2010 12:50 PM
Simple FIFO to I2S CPLD, for MCU players / reclocking KOON3876 Digital Line Level 21 19th September 2008 04:00 PM
asynchronous reclocking and low jitter clocks ash_dac Digital Source 3 8th February 2005 09:22 AM


New To Site? Need Help?

All times are GMT. The time now is 06:35 AM.


vBulletin Optimisation provided by vB Optimise (Pro) - vBulletin Mods & Addons Copyright © 2014 DragonByte Technologies Ltd.
Copyright ©1999-2014 diyAudio

Content Relevant URLs by vBSEO 3.3.2