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Old 18th April 2012, 11:03 AM   #391
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vzs zinsula,
thanks

.. so I have to wait Ian to modify FPGA logic ... the best way I understand

Ian
I'm in your hands..

Andrea
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Old 18th April 2012, 11:31 AM   #392
zinsula is offline zinsula  Switzerland
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Originally Posted by andrea_mori View Post
[..]Ian
I'm in your hands..[...]
Ti serve un piccolo aiuto
You need a little help from your friends
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Last edited by zinsula; 18th April 2012 at 11:38 AM.
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Old 18th April 2012, 06:39 PM   #393
vzs is offline vzs  Europe
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Originally Posted by iancanada View Post
[...]I attached simulation result waveforms generated by real synthesizable verilogHDL source code[...]
Hi Ian,
It looks promising. I also have some remarks:

Five jumper selectors
- it seems that beside jmpstopclk you used negative logic to set their function
- according to the simulations they look correct, but this negative/positive logic mixing is a bit confusing. Would be nice to be consistent and use either negative or positive logic for all

Data and clock lines for all three images
- is confusing that the MSB of the right channel starts with 0 while the MSB of the left channel with 1; so it looks like they are delayed by one clock, but probably not
- for stopped clock mode I also count +1 clock but I don't think this is an issue since only the last X bits will be transferred to the parallel DAC registers (after latch has gone low)

Concerning reclocking I share zinsula's opinion from #388.

A suggestion about board layout: it would be nice to be stack-able above the clock board - probably same size. If it's input would come from the FIFO board then the input connector could be in same position as on the clock board.

Thanks, Zsolt
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Old 18th April 2012, 11:34 PM   #394
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Quote:
Originally Posted by andrea_mori View Post
vzs zinsula,
thanks

.. so I have to wait Ian to modify FPGA logic ... the best way I understand

Ian
I'm in your hands..

Andrea
Hi Andrea, Don't worry about that, I'm the guy.
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Old 18th April 2012, 11:41 PM   #395
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Originally Posted by zinsula View Post
Ti serve un piccolo aiuto
You need a little help from your friends
... funny
I need more than a little help, I like this project but I like also my SM5842 and PCM63. They are waiting for the right implementation.
Any help would appreciate

Andrea
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Old 19th April 2012, 12:33 AM   #396
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Originally Posted by zinsula View Post
OK i checked the three examples. Some remarks

ContinueClk20bit:
Data seems OK
LE OK
Bit clock stop OK

Do I get it right, that if i see the jumper line, the jumper is OFF?
So, in this case,
jmp18bit=0, jmp20bit=1, jmp24bit=0, jmpstopclk=1 (why? it is not stopped); jmpaddclk=0

StopClkDelayLatch18bit:
Data seems OK
LE OK
Bit clock stop OK
BUT: i count 19 bits, not 18, therefore the MSB left data is 0, should be 1.

jmp18bit=1, jmp20bit=0, jmp24bit=0, jmpstopclk=0 (why? it is stopped); jmpaddclk=0


StopClkWith4More24bit:
Data seems OK
LE OK
Added clocks after LE going negative is OK (see my other post whether 2 or 4 clocks)
Bit clock stop OK
BUT: i count 25 bits, not 24, therefore the MSB left data is 0, should be 1.

jmp18bit=1 (?), jmp20bit=1 (?), jmp24bit=0 (?), jmpstopclk=0 (why? it is stopped); jmpaddclk=1

Ian, all in all that looks very good!
Thank you, Tino
Quote:
Originally Posted by zinsula View Post
I think, CLK and LLLR in your diagrams should be reclocked, as you did it on your clock board with separate flip-flops (pico gates?).
So we could "inject" the master clock from your clock board with the U.FL cable, isn't it?

Data is not that important, if you need it to reclock for timing/realignment purposes, the four data lines could be reclocked with a quad or whatever flip flop.

Thank you!
Quote:
Originally Posted by vzs View Post
Hi Ian,
It looks promising. I also have some remarks:

Five jumper selectors
- it seems that beside jmpstopclk you used negative logic to set their function
- according to the simulations they look correct, but this negative/positive logic mixing is a bit confusing. Would be nice to be consistent and use either negative or positive logic for all

Data and clock lines for all three images
- is confusing that the MSB of the right channel starts with 0 while the MSB of the left channel with 1; so it looks like they are delayed by one clock, but probably not
- for stopped clock mode I also count +1 clock but I don't think this is an issue since only the last X bits will be transferred to the parallel DAC registers (after latch has gone low)

Concerning reclocking I share zinsula's opinion from #388.

A suggestion about board layout: it would be nice to be stack-able above the clock board - probably same size. If it's input would come from the FIFO board then the input connector could be in same position as on the clock board.

Thanks, Zsolt
Hi guys, you made very good points

1, The one more clk, I call it "leading clock", is just for warm up the shift registers, avoid any potential glitch when switching from the stopping mode to the working mode. Logic wise, we don't need that additional clock. Any way, only last Nbit before the falling edge of latching signal will be latched into DAC, anything else will be shift away. Please let me know your point, leave it or remove it?

2, Each the jumper has a internal programble pull-up resister. So, the default logic is '1' if not be shorted to GND. I will leave the most possible default setting as 'open' to reduce the chance of 'jumping'. I'll have a very clear true table in the PDF file. Maybe, I need rename some of them to make the logic more clear.

3, PCM1702/04 need 2 and 4 clks, does that mean 4 more clks is safe for both of them?

4, As you all agree re-clock by the original mclk is a better solution than the second-generation sck, I'll inject the mclk from the clock board to make all FPGA logic synchronized with the original clock. In this case, the estimated Fmax could go up to 120MHz, finial performance will gain from this configuration.

5, On the simulation waveform, the 32bit I2S left channel data is 0xAAAAAAAA, while the right is 0x55555555, please just make sure the finial PCM Nbit data are correct correspondingly(MSB to MSB).

6, For sure, this small convertor board will be stacked over the clock board of the FIFO KIT with the same size and screw positions. I2S signals will be input directly form FIFO rather than from clock board to make the clock quieter . (we don't need the re-clocked I2S input, re-clocking will be made at finial stage)

7, Do you think this little convertor board need support an optional 'SONY' format beside the default I2S format?

Cheers,
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Old 19th April 2012, 03:19 AM   #397
1audio is offline 1audio  United States
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Originally Posted by iancanada View Post
And another thing is how do you think about the finial flip-flop re-clock function?
Without it the finial phase noise on the latching signal will be 12 dB more than the original mclk (because sck is a generated clk which is already 6dB more phase noise than the original mclk). (each signal generated by a clock will roughly 6dB more phase noise than that clock).
I'm not sure how you arrive at the +6dB phase noise from the logic. I would like to know.

In the testing I have done recently I'm seeing more issues around deterministic noise that random phase noise. I would use reclocking D latches, possibly the Potato stuff and run them on an isolated supply. It only takes a little supply noise to modulate a clock in a gate, especially when we are looking at -120 to -150 dB.
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Old 19th April 2012, 07:49 AM   #398
zinsula is offline zinsula  Switzerland
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Quote:
Originally Posted by iancanada View Post
[...]
1, The one more clk, I call it "leading clock", is just for warm up the shift registers, avoid any potential glitch when switching from the stopping mode to the working mode. Logic wise, we don't need that additional clock. Any way, only last Nbit before the falling edge of latching signal will be latched into DAC, anything else will be shift away. Please let me know your point, leave it or remove it?[...]
I agree with you and Zsolt that as only the last n bits will be clocked in before latching. You clearly know more about all that high speed logic stuff and if you think that it has some advantages, leave it.

Quote:
Originally Posted by iancanada View Post
[...]
2, Each the jumper has a internal programble pull-up resister. So, the default logic is '1' if not be shorted to GND. I will leave the most possible default setting as 'open' to reduce the chance of 'jumping'. I'll have a very clear true table in the PDF file. Maybe, I need rename some of them to make the logic more clear.[...]
No problem. It was just me which did not get naming and status of the bits. As long as the combinations are safely described and not ambiguous (logic wise) it's OK.

Quote:
Originally Posted by iancanada View Post
[...]
3, PCM1702/04 need 2 and 4 clks, does that mean 4 more clks is safe for both of them?

[...]
This is a though one for me. I believe using 4 more clocks will be safe for both. As the DATA and LE lines are quiet anyway during conversion, I believe there is not much performance loss.

Quote:
Originally Posted by iancanada View Post
[...]

4, As you all agree re-clock by the original mclk is a better solution than the second-generation sck, I'll inject the mclk from the clock board to make all FPGA logic synchronized with the original clock. In this case, the estimated Fmax could go up to 120MHz, finial performance will gain from this configuration.[...]
Very good. Will you use single flip flops (Potato?) for the sensitive clocks (LE and Bit clock?)


Quote:
Originally Posted by iancanada View Post
[...]

5, On the simulation waveform, the 32bit I2S left channel data is 0xAAAAAAAA, while the right is 0x55555555, please just make sure the finial PCM Nbit data are correct correspondingly(MSB to MSB).[...]
Actually, it helped me identify if all is OK (L/R difference)

Quote:
Originally Posted by iancanada View Post
[...]
6, For sure, this small convertor board will be stacked over the clock board of the FIFO KIT with the same size and screw positions. I2S signals will be input directly form FIFO rather than from clock board to make the clock quieter . (we don't need the re-clocked I2S input, re-clocking will be made at finial stage)[...]
Good, so the (dual) clock board is needed to select the correct clock freq and to provide the clean MCLK?
Will we still have the actual functionality on the dual clock board, i.e. the indication of fs and MCLK multiplicator?

Quote:
Originally Posted by iancanada View Post
[...]
7, Do you think this little convertor board need support an optional 'SONY' format beside the default I2S format?
[...]
Do you mean if you feed the FIFO with Sony format? Is that word length 24 bit, left justified, MSB first after word clock change, and Word Clock high = left channel?
Or do you mean that it should output Sony format, to feed eg. Andrea's SM5842?

All in all, great job Ian. thank you.
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Last edited by zinsula; 19th April 2012 at 08:10 AM.
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Old 19th April 2012, 08:09 AM   #399
zinsula is offline zinsula  Switzerland
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Quote:
Originally Posted by 1audio View Post
[...]I would use reclocking D latches, possibly the Potato stuff and run them on an isolated supply. It only takes a little supply noise to modulate a clock in a gate, especially when we are looking at -120 to -150 dB.
Yes, using separate D-Flip-Flops (i mean using only one Flip Flop per case) for the important signals will allow to decouple their supplies, minimizing the crostalk on the supply line. Inductor will help to isolate them from each other.

As i understood the Potato stuff, it is about them using balanced signals, which would result in less power supply modulation. As in our beloved balanced amps or preamps....
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Last edited by zinsula; 19th April 2012 at 08:12 AM.
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Old 19th April 2012, 08:19 AM   #400
vzs is offline vzs  Europe
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Quote:
Originally Posted by iancanada View Post
1, The one more clk, I call it "leading clock", is just for warm up the shift registers, avoid any potential glitch when switching from the stopping mode to the working mode. Logic wise, we don't need that additional clock. Any way, only last Nbit before the falling edge of latching signal will be latched into DAC, anything else will be shift away. Please let me know your point, leave it or remove it?
I would leave the "leading clock" for the reasons you mentioned, better to be on the safe side.

Quote:
Originally Posted by iancanada View Post
3, PCM1702/04 need 2 and 4 clks, does that mean 4 more clks is safe for both of them?
With 4 trailing clocks only PCM1702 would benefit of the stopped mode operation while for PCM1704 would be similar to continuous clock mode.
As PCM1704 is the newer and seems to be used by more diyers I would better support this - so to have 2 trailing clocks. But it's all one for me.

Quote:
Originally Posted by iancanada View Post
7, Do you think this little convertor board need support an optional 'SONY' format beside the default I2S format?
You would make fellow diyer andrea_mori happy

If you add another output format I have some arguments for the Left Justified over Sony Format:
- as I understood Andrea wants to connect the FIFO between a CD-Pro and his Sony Format input DAC board. As the CD-Pro outputs 16bit I2S you would have to add 16bit support to the converter to output a correct right justified format for him
- Left justified differs from I2S very slightly: latch should be negated and shifted with one clock - so needs less logic to implement
- digital filters from NPC, TI/BB, PMD all support Left Justified with multiple bit lengths, while Sony Format is supported only for 16bit data; except for NPCs
- the downside is that Andrea would have to make some minor pcb adjustments to set his board for Left Justified format - but hey, this is diy
All in all I'm fine with or without it.

Thanks, Zsolt

Last edited by vzs; 19th April 2012 at 08:25 AM.
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