Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

[zinsula]

Originally Posted by andrea_mori

[...]
BTW do you think that I can feed 5842 using this schematics?
[...]

Andrea, I don't think so. The schematic is strange anyway, Pin 5 and 10 should not be left open AFAIK.
To feed SM5842, you'd need to delay WCK one bit clock (could be done before FIFO), then distribute the data to DIL and DIR, invert the WCK (it is exactly opposite polarized than I2S) or cheat, by feeding DIR with left data and vice versa. Also, in that case, you have to feed the left DAC with DOR and vice versa.

32 bit frames from I2S should not be a problem though.

[iancanada]

Originally Posted by andrea_mori

Ian,

I would like to order FIFO kit, but I'm a bit confused.
As I said I want to feed FIFO kit directly from CD PRO I2S, then I would like to take I2S output and MCLK and feed digital filter NPC SM5842.
You tell me that SM5842 do not accept I2S format data, while Rregal in a previous post said that it can do it.
I found on the web the attached schematics that interface I2S with 5842, so I believe you're right.

BTW do you think that I can feed 5842 using this schematics?
If yes, do I need FIFO board only?
What frequency oscillator?

Anyone can help me?

Thanks in advance
Andrea

The schematic did show the DIR. Since all DIR support left justified format, I suspect that is. If me FIFO could support this format, you don't need anything else to feed signals into 5842.

[vzs]

Originally Posted by zinsula

So you mean to have it as an optionally selectable format, as would be the stopped clock operation?
Then it's OK of course :-)

Of course optionally selectable; seems it will support many.

[andrea_mori]

Originally Posted by zinsula

Andrea, I don't think so. The schematic is strange anyway, Pin 5 and 10 should not be left open AFAIK.
To feed SM5842, you'd need to delay WCK one bit clock (could be done before FIFO), then distribute the data to DIL and DIR, invert the WCK (it is exactly opposite polarized than I2S) or cheat, by feeding DIR with left data and vice versa. Also, in that case, you have to feed the left DAC with DOR and vice versa.

32 bit frames from I2S should not be a problem though.

Zinsula,

it seems that 5842 is feeded like Sony data format.
But quad flip-flop HC175 do not act what you say?

[iancanada]

Hi zinsula, Hi vzs,

I attached simulation result waveforms generated by real synthesizable verilogHDL source code. Please note the five jumpers. Three of them for selecting data length; one of them to decide if going with stopping clock function; If stoping clock function is enabled, the another one selecting if delay the latching signal (for ASD18XX and PCM63) or add four more clocks without delay the latching signal (for PCM1702/4).

Me too got a bit confusing on the PCM1702/04 timing, please confirm the added clock number is 4 (now is 4) or 2.

And another thing is how do you think about the finial flip-flop re-clock function?
Without it the finial phase noise on the latching signal will be 12 dB more than the original mclk (because sck is a generated clk which is already 6dB more phase noise than the original mclk). (each signal generated by a clock will roughly 6dB more phase noise than that clock).

* Please find the file names of each attached pictures for what they are.

Small project with a lot of details .

[zinsula]

Originally Posted by iancanada

[...]Me too got a bit confusing on the PCM1702/04 timing, please confirm the added clock number is 4 (now is 4) or 2.[...]

Hi Ian,
PCM1704 needs 2 clocks, PCM1702 needs 4 clocks, see the attached descriptions from those datasheets.

If there is to choose which one, i'd say PCM1704, as I have the impression that more people uses them. But I really do not want to press decision on this one, I do not have neither of those DAC's.

[zinsula]

Originally Posted by iancanada

[...]I attached simulation result waveforms generated by real synthesizable verilogHDL source code. Please note the five jumpers. Three of them for selecting data length; one of them to decide if going with stopping clock function; If stoping clock function is enabled, the another one selecting if delay the latching signal (for ASD18XX and PCM63) or add four more clocks without delay the latching signal (for PCM1702/4).[...]

OK i checked the three examples. Some remarks

ContinueClk20bit:
Data seems OK
LE OK
Bit clock stop OK

Do I get it right, that if i see the jumper line, the jumper is OFF?
So, in this case,
jmp18bit=0, jmp20bit=1, jmp24bit=0, jmpstopclk=1 (why? it is not stopped); jmpaddclk=0

StopClkDelayLatch18bit:
Data seems OK
LE OK
Bit clock stop OK
BUT: i count 19 bits, not 18, therefore the MSB left data is 0, should be 1.

jmp18bit=1, jmp20bit=0, jmp24bit=0, jmpstopclk=0 (why? it is stopped); jmpaddclk=0


StopClkWith4More24bit:
Data seems OK
LE OK
Added clocks after LE going negative is OK (see my other post whether 2 or 4 clocks)
Bit clock stop OK
BUT: i count 25 bits, not 24, therefore the MSB left data is 0, should be 1.

jmp18bit=1 (?), jmp20bit=1 (?), jmp24bit=0 (?), jmpstopclk=0 (why? it is stopped); jmpaddclk=1

Ian, all in all that looks very good!
Thank you, Tino

[zinsula]

Originally Posted by iancanada

[...]And another thing is how do you think about the finial flip-flop re-clock function?
Without it the finial phase noise on the latching signal will be 12 dB more than the original mclk (because sck is a generated clk which is already 6dB more phase noise than the original mclk). (each signal generated by a clock will roughly 6dB more phase noise than that clock).[...]

I think, CLK and LLLR in your diagrams should be reclocked, as you did it on your clock board with separate flip-flops (pico gates?).
So we could "inject" the master clock from your clock board with the U.FL cable, isn't it?

Data is not that important, if you need it to reclock for timing/realignment purposes, the four data lines could be reclocked with a quad or whatever flip flop.

Thank you!

[vzs]

Originally Posted by andrea_mori

it seems that 5842 is feeded like Sony data format.
But quad flip-flop HC175 do not act what you say?

I believe the pin description table in SM5842 manual is screwed up a bit: see page 3, explanation of pins 5,10 - there is no such pin like IW2N/DIL or IW1N/DIR and in the explanation of pin10 it would be logical to mention INF1N not INF2N.

Indeed, your schematic from #375 is configured for Sony format: INF1N (pin4) is LOW
But if this format is selected the bit length should be selected as well: see description pin5, 10 - but in the schematics these pins were left open-this is not correct


I think zinsula suggested to modify the input format from Sony-format to left justified-LR data alternating and he suggested a simple way to change I2S format to left justified format. For this format you would have to make INF1N HIGH and DI/INF2N LOW (your data input being now IW1N/DIL and IW2N/DIR)

If Ian will manage to squeeze the Left-Justified format into its converter you will not need the I2S-to-left justified logic suggested by zinsula.

The 75VHC175 flip-flops simply reclocks the data comming out from SM5842 with the master clock.

[zinsula]

Originally Posted by andrea_mori

[...]it seems that 5842 is feeded like Sony data format.[...]

Well then it's OK and you do not have to alter the data.
But I thougt your transport is putting out I2S? Sony format is not I2S!

Originally Posted by andrea_mori

[...]But quad flip-flop HC175 do not act what you say?

No, it is just there for reclocking.

What i said is that if you have true I2S, you have to modify the data before SM5842.
In your schematic, i see nothing in front of SM5842.
74VHC175 is between SM5842 and DAC's (are these PCM63?)