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Old 14th April 2012, 12:15 PM   #351
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Hmm, I picked up a 24/96k usb to i2s adapter. Will the Fifo & dual clocks simply reclock what goes into the buffer at a higher rate?

Or would I need a 24/192 usb to i2s adapter for that?

Last edited by merlin2069er; 14th April 2012 at 12:20 PM.
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Old 14th April 2012, 05:08 PM   #352
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its a reclocker, not a resampler and its capable of up to 192 (with the right clocks and higher with some mods perhaps), it is not set at an upsampled rate of 192, it will simply output what is input afaik
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Old 14th April 2012, 05:20 PM   #353
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Hey Ian, I think it should be noted, given that we are mostly terminal tweeters in this thread, that the u.fl cables and sockets (mostly cables I think) are only useful for a limited number of connections/disconnections and less if you dont use a suitable tool for that. perhaps I could make the suggestion for an instruction in the manual for users to use the ribbon/molex type connectors and cables that are in parallel for the testing phase and only use the u.fl once layout and testing is complete?
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Old 14th April 2012, 09:15 PM   #354
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Quote:
Originally Posted by analog_sa View Post
Would it be possible to add 24 bit as well. Please
Yes, it's possible. Seems I need cover 24bit.
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Old 14th April 2012, 09:49 PM   #355
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terminal tweekers, not tweeters i've never tweeted anything in my life lol
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Old 14th April 2012, 10:00 PM   #356
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Quote:
Originally Posted by qusp View Post
Hey Ian, I think it should be noted, given that we are mostly terminal tweeters in this thread, that the u.fl cables and sockets (mostly cables I think) are only useful for a limited number of connections/disconnections and less if you dont use a suitable tool for that. perhaps I could make the suggestion for an instruction in the manual for users to use the ribbon/molex type connectors and cables that are in parallel for the testing phase and only use the u.fl once layout and testing is complete?
That's good suggestion. I'll keep in mind in case I update the doc .
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Old 14th April 2012, 10:31 PM   #357
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cool, yeah ive never been faced with the destruction of one other than ones ive used on prototypes for shielded power connections, but it just occurred to me, since i'm doing more connect/disconnect cycles now that I have more devices using them.

For now i've gone back to using the molex connectors until ive reached a semi permanent layout. they are more robust than the manufacturer claims, but still best to avoid needless cycles and definitely the usefulness of the tool or a diy equivalent is a must.

even something as simple as levering it up with a small blade from right next to the socket while pushing down on the strain relief so it pops straight up rather than rolling over, if you know what I mean. an actual tool or equivalent is preferred though of course
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Old 14th April 2012, 11:36 PM   #358
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Originally Posted by iancanada View Post
Yes, it's possible. Seems I need cover 24bit.
Yes please -I think your FIFO right justified 24bit output plan will be widely appreciated.

There are many PCM1704 based DAC's around, so a 24bit right justified low jitter feed will be popular for modding legacy machines, currently limited by SPDIF interfaces and pre-ringing hardware filters like the DF1704.

I wonder how high a sampling rate you can design for?

The PCM1704 data sheet states "supports 8X oversampling at 96kHz" = 768kHz.

If you can manage higher sample rates it will allow computer based audio users to use a variety of oversampling software filters. This could allow for a simple mod to make a huge improvement in the sound quality of PCM1704 DAC's.

If you can add USB input it would be perfect for me?

Thanks for your amazing work so far.
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Old 15th April 2012, 12:31 AM   #359
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Default I2S to AD18XX/PCM63/PCM1704 convertor

Quote:
Originally Posted by vzs View Post
Taking into account zinsula's suggestions of delaying LE the stopped clock timings could be could be smtg like that:
Quote:
Originally Posted by zinsula View Post
For PCM1702, Datasheet states the following:


So I believe it needs 4 clocks.

There are so many different requirements, it's kinda difficult to have all OK for all DAC's.
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Originally Posted by Nikola Krivorov View Post
24 bit AND working with the 1704/02 would be nice... Could somone build it, please...
Make sense. I suspect, inside AD18xx, there are just two shift registers and two latching registers, PCM63, maybe. But for PCM17xx, they need a couple of addition clks for some different constructions.

It seems we should:
1. Supporting 16bit, 18bit, 20bit and 24bit format with selectable setting jumpers.
2. Including a clock function jumper to enable or disable the 4 clks after negative edge of latching,in order to be compatible with pcm17xx.
3. For AD18XX, do not compromize with PCM17xx. Delay the latching and stop the clock after shifting.

I attatched the updated timing plots, taking example for both AD1865 and PCM17xx. Let me know for any problem.

*please don't care about the LL,LR signals at the next word, I forgot changing them on the plots.

Nice weekend.
Attached Images
File Type: jpg I2StoAD1865DelayLatch.jpg (95.1 KB, 514 views)
File Type: jpg I2StoPCM1704Conversion.jpg (98.4 KB, 510 views)
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Last edited by iancanada; 15th April 2012 at 12:45 AM.
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Old 15th April 2012, 01:05 AM   #360
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Quote:
Originally Posted by kazap View Post
Yes please -I think your FIFO right justified 24bit output plan will be widely appreciated.

There are many PCM1704 based DAC's around, so a 24bit right justified low jitter feed will be popular for modding legacy machines, currently limited by SPDIF interfaces and pre-ringing hardware filters like the DF1704.

I wonder how high a sampling rate you can design for?

The PCM1704 data sheet states "supports 8X oversampling at 96kHz" = 768kHz.

If you can manage higher sample rates it will allow computer based audio users to use a variety of oversampling software filters. This could allow for a simple mod to make a huge improvement in the sound quality of PCM1704 DAC's.

If you can add USB input it would be perfect for me?

Thanks for your amazing work so far.
Thanks kazap,

Simultion shows the MCLK of my FIFO could go upto 125Mhz. I did a real loop testing with a 100Mhz MCLK a couple of weeks ago. Within 2 hours, I didn't catch any error. MCLK was 256Fs and Fs was 390.625Khz. So, if with 128Fs MCLK, theoretically it could go up to 768Khz, but I don't have anything to test so far. Do you know which USB could go up to 768Khz?

Have a good night.
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