Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter - Page 166 - diyAudio
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Old 8th December 2012, 04:15 AM   #1651
qusp is offline qusp  Australia
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the thin film caps are pretty much the most linear cap you can find, unfortunately not available in large values, but for close HF decoupling on the Si570 they should be perfect. hopefully one day they will make them in larger 10-100nF sizes.

are you also playing with building planar capacitance into the PCB design itself?

is the pattern on the tps regulator board 7343 size? I have used the tantalum/polymer caps you have tried (the orange ones) and much prefer the SP-CAP, as you see in the part I linked, ripple rejection is very good and 5-7mOhms impedance for a ~100F cap is pretty excellent.
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Old 8th December 2012, 09:45 AM   #1652
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Speaking of Murata products, I bought a few of these LC combined parts at some point but didn't have a chance to test them yet.
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Old 8th December 2012, 11:00 AM   #1653
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Ian is already using a few parts from that range in the fifo
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Old 8th December 2012, 11:26 AM   #1654
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Good to know!
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Old 9th December 2012, 12:43 PM   #1655
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I'm aiming to use the tps7a4700 evalboard in a project and is looking to replace the X5R caps with Panasonic SP's.
After some handywork this is what should be the available space if mounted next to each other but most likely there will be some spacing.

Not shure that this is the right thread for this but since there is disscusion about both the caps and the reulator so........

For C1 and C5-9 there will be panasonic sp caps. I'm not shure about C2, suggestions anyone ? Probably another sp I think.


This comes from the user guide:
Quote:
The TPS7A4700 is designed and characterized for operation with ceramic capacitors of 10 μF or greater at the
input and output. Optimal noise performance is characterized using a total output capacitor value of 50 μF
Nothing said about input capasitance values, there is 47+10uf mounted now.
Is there any reason to increase on that ?

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Old 9th December 2012, 01:26 PM   #1656
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no its not the correct thread for discussion of the regulator on the demo board to power a completely different DSP/DAC to what is under discussion here.... which is not even a dac, nor is the board under discussion the regulator demo board

I must admit to being confused with your use of this regulator after a raw supply and before placid shunt regs, did you not buy the correct voltage power transformer? adding all this extra caps for low impedance storage when you are following with a shunt reg makes no sense to me; it seems like you are replacing proper measurement and design with overkill

Last edited by qusp; 9th December 2012 at 01:34 PM.
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Old 9th December 2012, 01:29 PM   #1657
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It's in the pdf documentation for the eval board on page 2

NOTE: The positive input lead and ground return lead from the input power supply should be twisted
and kept as short as possible to minimize EMI and source inductance. Additional bulk
capacitance in the form of a Tantalum cap (47 F; 35 V) has been added to the EVM at C1
to counter source inductances that may cause ringing on the load transient waveform during
higher current transients. This bulk capacitance should not be necessary in a typical
application circuit.
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Old 9th December 2012, 02:13 PM   #1658
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Quote:
Originally Posted by qusp View Post
no its not the correct thread for discussion of the regulator on the demo board to power a completely different DSP/DAC to what is under discussion here.... which is not even a dac, nor is the board under discussion the regulator demo board

I must admit to being confused with your use of this regulator after a raw supply and before placid shunt regs, did you not buy the correct voltage power transformer? adding all this extra caps for low impedance storage when you are following with a shunt reg makes no sense to me; it seems like you are replacing proper measurement and design with overkill

Point taken, I'll start a thread for this specific project. You're welcome when posted.
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Old 9th December 2012, 02:16 PM   #1659
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Sorry, if I cross threaded subject here with my IV stage thing...

Last edited by Fridrik; 9th December 2012 at 02:21 PM.
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Old 10th December 2012, 05:37 PM   #1660
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Default Master clock

Just another option, this is an OCXO from HCD, and its excellent performance in phase noise.
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File Type: jpg HCD_OCXO.jpg (79.1 KB, 410 views)
Attached Files
File Type: pdf Phase Noise - 04.12.12.pdf (203.8 KB, 127 views)
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