Asynchronous I2S FIFO project, an ultimate weapon to fight the jitter

I did a little toy. I connected an A123 LiFeP04 battery to a 14pin IC socket. This configuration works as an adapter bypassing the power of the PCB. So the battery could power the XO oscillator directly from the socket as a reference without changing any other function. The output voltage of LiFeP04 is just around 3.3V. This little toy is really working.

I’m looking for power supply which comes with equal or closing low noise performance than a batter. But I’m not lucky so far. It’s really hard to measure if the PUS output noise is low, especially within wide bandwidth. However, by compare with the battery reference, it’s very easy to tell which one is better. I did some research by making use of this reference, the result was very interesting.

It’s also available that replacing the battery with other PSU to be evaluated.

hey mate, any chance you have some of these little dip pcbs around? I should have asked for a few, i'll send you some coin and money for postage.

where did you get the A123? that particular model is the most pirated and if you didnt buy it direct from A123 or an official a123 reseller, of which there are maybe 2, then you have fake or grey market there.
 
any chance you have some of these little dip pcbs around? I should have asked for a few, i'll send you some coin and money for postage.

You mean the little adapter PCB? It works very well with CCHD975, otherwise you have to solder flying wire. I ordered 20 of them for prototype, may still have something left. will throw a pair of them to you. Don't worry about the postage, buy me a cup of coffee :) .

Ian
 
hehe latte fine? yes those are the ones, they should fit the other Crystek (sp) parts too. flying wires on a master clock seems about the worst thing you could do. while you were at it, did you get a chance to scope out these sorts of differences? maybe these things arent all as meaningful as you would think.
 
Simulating Demian’s regulator

Demian posted a low noise regulator here: http://www.diyaudio.com/forums/digital-line-level/192465-asynchronous-i2s-fifo-project-ultimate-weapon-fight-jitter-11.html, which was specialized for powering the oscillators.

I did some quick simulation yesterday. I was mainly focused on PSRR simulation. I don’t expect the load response performance because of the LPF on the feedback pass.
1. The first simulation shows the PSRR was 1dB at 1Hz and 10dB at 10Hz. The voltage drops on Q1 was too low and Sziklai pair didn’t run at optimized range.
2. I raised the DC input to 7V, see the second simulation, the PSRR went 90dB at 1Hz, very good low range. However, it dropped to 52dB around 12Hz. There might be a pole.
3. I remove C5, see the third simulation. We got perfect PSRR, greater than 80dB throughout 1Hz to 1.1 MHz.
4. I got the noise simulation spectrums, yes, it’s very low.
5. The power up time was 600ms, any way, we need making some compromise.

Some possible notes,
1. The main noise contribution would be the input, especially for the high frequency noise, because the PSRR start dropping below 60dB from 6 MHz.
2. Only suitable for static load (resistor load). The LPF corner frequency is too low.
3. Be careful the low frequency (below LPF) 1/f noise from voltage reference, I don't think it was included in the SPICE model.

Ian
 

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The model for the TL431 will oscillate at low frequencies if C5 is less than 20 uF if present. The actual part in this application shows no signs of oscillation. The model is not fully representative of the part. It might be better to think of the TL431 as a servo steering the output voltage to the target. The circuit works fine with a resistor divider for the reference voltage, but won't compensate for line, load and thermal effects.

It does work well with a 5V input. I'm surprised you are getting different results. It may be the TL431 model. I can assure you it works pretty well when built with the parts as shown. I'll play with the sym some more and also try to get a working regulator to misbehave.
 
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Updated circuit model

I have updated the circuit adding the stabilization necessary for the LT1431 model to get it to work. I'll check the real circuit later today to see if there is evidence of the instability. In this form the isolation is quite good up to 1 MHz. Above that the capacitance across the active devices shunts any isolation. Small inductors or ferrite beads would be the appropriate enhancement.

Changing R3 from 100 Ohms to 2200 Ohms doesn't degrade the performance and reduced the extra current significantly (-8 mA). The output impedance goes up but that isn't important for powering a crystal oscillator.

I don't know if the file is compatible with your simulator but the changes should be pretty easy to map across.

There is more discussion about this circuit here: http://www.diyaudio.com/forums/digital-source/185761-open-source-usb-interface-audio-widget-103.html#post2884358
 

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It does work well with a 5V input. I'm surprised you are getting different results. It may be the TL431 model. I can assure you it works pretty well when built with the parts as shown. I'll play with the sym some more and also try to get a working regulator to misbehave.

Thanks Demian. The simulation result didn't mean it not work with 5V input. It dose work! The only thing is with 5V input, the line regualtion performance is not that excellent. But if we increase the voltage a little bit, says 7V (actuall 6V is already OK), the line regulation is gonna be much much better(PSRR above 80dB from 0-1.1MHz). I use Multisim, the model might be a bit different from LTspice, but won't be too much. I like the idea, reducing the noise by LPF the voltage reference which was suspected to be the biggest noise source. But all the SPICE noise analysing is based on the noise model of transistors and resisters. It would be very hard to get accurate noise simulation reslut if TL431 model is not based on the real internal components and circuits. Ian
 
Hey Ian,
I have some question regarding interfacing your board with my system.
As my AD1865 DAC needs a 18bit LSBJ stream I'm using a simple converter board with a shifter logic like this: link to convert 32bit I2S to 18bit LSBJ. Basically data is shifted with 13 clocks.

- As I don't want to use double output reclocking -first with your board then with mine - I thought I could create a small data-shifter board and plug it between the FIFO board and single XO clock board, therefore the clock board would receive an LSBJ stream with data shifted. Am I right that the reclock part does not care about what it reclocks, so this approach can work?

- How does the FIFO board receives the master clock from the single XO clock board?
- What is the reclock frequency: 128Fs or 256Fs?

Thanks!
Zsolt
 
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Hey Ian,
I have some question regarding interfacing your board with my system.
As my AD1865 DAC needs a 18bit LSBJ stream I'm using a simple converter board with a shifter logic like this: link to convert 32bit I2S to 18bit LSBJ. Basically data is shifted with 13 clocks.

- As I don't want to use double output reclocking -first with your board then with mine - I thought I could create a small data-shifter board and plug it between the FIFO board and single XO clock board, therefore the clock board would receive an LSBJ stream with data shifted. Am I right that the reclock part does not care about what it reclocks, so this approach can work?

- How does the FIFO board receives the master clock from the single XO clock board?
- What is the reclock frequency: 128Fs or 256Fs?

Thanks!
Zsolt

Hi Zsolt,
I like AD1865. My PCM7040 sounds perfect!
I analyzed your schematics, the answer is yes. You could insert your converter boare between fifo and single clock board. The default reclock frequency is 256Fs for the single clock board. FIFO receive the master clock from the FFC/FPC interface cable. You are right, my reclock circuit reclock signals by the master clock no matter what they are. Logiclly, there is no difference reclock at 128Fs or 256Fs. However, reclock by master clock directly will have less jitter.
Have a nice weekend.
Ian
 
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Hi Zsolt,
I like AD1865. My PCM7040 sounds perfect!
I analyzed your schematics, the answer is yes. You could insert your converter boare between fifo and single clock board. The default reclock frequency is 256Fs for the single clock board. FIFO receive the master clock from the FFC/FPC interface cable. You are right, my reclock circuit reclock signals by the master clock no matter what they are. Logiclly, there is no difference reclock at 128Fs or 256Fs. However, reclock by master clock directly will have less jitter.
Have a nice weekend.
Ian

So you do mean this unit outputs true Phillips 16+16 I2S (if it is input) as opposed to the difficult 32x32bit wordlength format that has recently come about with most of the usb implementations ?
 
So you do mean this unit outputs true Phillips 16+16 I2S (if it is input) as opposed to the difficult 32x32bit wordlength format that has recently come about with most of the usb implementations ?

Hi regal,
This I2S FIFO accepts true 16bit to 32bit I2S input range (actually sck input from 32fs to 64fs). Internally, the FIFO memory is true 32bit processing. Output sck is 64fs (I2S standard, same as most DIRs). No problem if you feed true 32bit I2S, bit perfect confirmed.
Have a nice weekend.
Ian