New AK4396 DAC board design support needed

[SunRa]

Hi all,


With the arrival of new USB interfacing options such as the Exa devices, hiface and musiland, I have decided to try and design a DAC board, mainly for educational reasons.

I already have a (breadboards) DAC around PCM2706, too ugly to show it here, which amazed me by actually making music, therefore I have the means of taking an I2S signal for testing the new DAC until the exa device becomes available.




Regarding the board I am trying to layout, the only interesting design details, not used in the datasheet, are the following two:

1. Dedicated (digital and analogic) low noise IC: LT 1763. I intend to replace these with some other ones: LP5900, (6uV vs 20uV RMS noise figures) selected with the help of glt, our diyaudio member behind hifiduino. The reason for not using them from the start is that they need an even smaller, more difficult to solder package, and I am not ready for this yet.
2. Inductors placed on each rail, between the decoupling capacitors. I've chosen for this some 805 pads, not sure if I can find something usefull at this size.

Question 1: I've used a single voltage regulator for both AVSS and Vref, do you believe I should treat these differently? Should the AVSS have a more advanced regulator (Buffalo dac uses some op-amps regulators if I recall correctly). And should I use separate regulators for AVSS and Vref, or this is not recommended?
Question 2: Can you please recommend some good beads for the decoupling parts? I really don;t know what characteristics these inductors should have.




Layout goals:
The routing done above is not the final one, and is not very well thought about. In fact is just for having something to upload and start with. I've done only to route the input wires, to make sure they stay on the top plane and then hit the autorouter.

I plan to:
- keep all the signal wires (except the control ones, which I am not sure I need them), on the top plane.
- pour a groundplane on the top. The high frequency signal wires should be separated by parts of the groundplane.
- pour a bottom power plane, at least across some parts of the PCB, and connect this with the top parts with vias.

Question 3: I've managed to place the decoupling capacitors prety close to the power pins, should I make an extra efforts and place some of the components (the inductors for example) on the bottom plane for even smaller distances?

Question 4: How do I pour a plane in Eagle? I used the polygon tool, and gave the polygon the same name (GND) with the net I was interested to connect with, using the tool name. I selected an Isolate value of 0,01. However the plane just won't render, as you can see in the above image. Any ideas?

Any other suggestions are welcomed!

[Gluca]

AKM tech support suggested me to avoid inductors after the local regulator to improve distortion figures.

[SunRa]

Thanks Gluca,

I wonder why is that and if it's specific to AK4396.

[SunRa]

It seems this generation of dacs is not that attractive anymore .

Still, if someone knows how to resolve the problem of pouring a polygon plane, it would be great..

[SunRa]

Just a short folow-up, I've managed to resolve the issue of polygon pouring, it seems that, eh, I was not hitting ratsnest button after pouring. The only tutorial in which I found this recommendation was HERE. It has a wealth of good info, regarding planes in eagle.

I've also made some changes on the board layout, but it's far from over. I gave more importance to the digital inputs and the analog outputs as you can see, but the digital control lines are snaking around the board in the left side and I don;t like that.

Also I'll digg in the datasheet to make sure I need all that control. As far as I can remember the dac automatically sets the fs by looking at the ratio between the lrclk and bitclock, so those lines probably won't be needed, except diff0 and diff1.

The priority is however optimizing the power lines on the bottom layer, and I was wondering if it would be ok to split the plane in three: VBUS, for the unregulated power line feeding the regulators, vreg 1 and vreg2 for the regulated lines that feed the decoupling capacitors for AVSS and DVSS.

[SunRa]

It seems rather quite around here, so I'll jump in some additional info. First of all I've noticed a huge layout problem around c11 and l3, the live track is surrounding all those components instead of taking the short route. However, I will proceed as on Tent's article on decoupling:

- The L bead will be as close as possible to the input dc pin.
- The unpolarized C will be as close as possible to the ground pin.
- Ground plane on the top surface.
- No power planes whatsoever, as they act as antennas according to Mr. Tent

Question: With the power plane out, there's a lot of room left on the bottom plane, would another ground plane hurt anything? Will some kind of parasitic capacitance occur between the two? I plan to place lots of vias between them if I proceed that way. What do you think?

[singa]

Hi, For someone attempting to design a pcb he should already know the
basics and as you have identified some faults you should go ahead and
redo the pcb.Asking if one should use another ground plane when you know
in electrical theory even two trace side by side will create a capacitance is
asking a silly question.Solve problems when you encounter them,then you will
learn along the way.After all this is suppose to be to be educational right? So
keep it simple and you will probably succeed. singa

[marce]

I would have a look at this, it shows how digital signals couple with the ground plane. I would route the board with the bottom layer as near a full ground as possible, ie minimise track and slots on that layer. Further more I would not route any signals over any slots in the ground plane.
I would also cover as much of the board as possible with ground pours, if they are tied together with vias they aint gonna cause a problem.
I would be interested in Mr Tents articles on power planes and de-coupling!

[5th element]

From recent personal experience I can say that having a ground plane directly beneath the DAC chip on the copper top was required for distortion performance.

The main ground plane is the copper bottom and is completely uninterrupted, however on it's own, it wasn't enough, without the copper directly beneath the chip on the copper top, performance was significantly degraded. We're talking going from 0.02% to 0.0008% @ 192khz, or 0.002% to 0.0005% @ 48khz.

Marce, it looks like you intended on providing a link with your previous post?

Edit - SunRa, have you tried printing out the design and checking to see if the printer can resolve the fine separation between the tracks on the DAC chip? With Eagles default package size the printer I've got joined them all together, I had to resize the pads for it to work well. For SSOP packages I use 0.38mm width pads.

[prairiemystic]

The LT1763 need pin 1+2 tied (out+sense) together!