Late Link, sorry.
http://www.x2y.com/filters/TechDay0...log_Designs_Demand_GoodPCBLayouts _JohnWu.pdf
I should have also said that when using SMD components on a doublesided board, the ground is better on the bottom, and routing on the top, as you dont split up the ground as much.
http://www.x2y.com/filters/TechDay0...log_Designs_Demand_GoodPCBLayouts _JohnWu.pdf
I should have also said that when using SMD components on a doublesided board, the ground is better on the bottom, and routing on the top, as you dont split up the ground as much.
@marce,
Thanks for the link, not only is informative but there's some data there I've never thought to be found out in the wild.
@singa,
The idea is great, however I should point that I was trying to follow Tent's recommendation regarding the placement of the caps and I gave less attention to the distance of the dc track and I've tried to minimize the distance between the ground pin of the dac and the ground connection of the capacitor, as below:
Probably rotating the capacitors as you suggested would further shorten that distance but the dc track will be longer so I find this a good compromise.
5th element, I'll try just that it seems likely to work.
In the meanwhile I decided to let access to the additional pins I was not sure I need, just as a measure in case I need to debug/configure something. The next version will consider the findings I'll make after building this.
Thanks for the link, not only is informative but there's some data there I've never thought to be found out in the wild.
@singa,
The idea is great, however I should point that I was trying to follow Tent's recommendation regarding the placement of the caps and I gave less attention to the distance of the dc track and I've tried to minimize the distance between the ground pin of the dac and the ground connection of the capacitor, as below:
An externally hosted image should be here but it was not working when we last tested it.
Probably rotating the capacitors as you suggested would further shorten that distance but the dc track will be longer so I find this a good compromise.
5th element, I'll try just that it seems likely to work.
In the meanwhile I decided to let access to the additional pins I was not sure I need, just as a measure in case I need to debug/configure something. The next version will consider the findings I'll make after building this.
As far as I can see, the only thing that requires reconfiguring, during hardware control, is the rate the DAC works at, otherwise you're stuck to one specific band of sampling frequencies. Although it is certainly a good idea to provide access to all the other pins until you've got the design completely sorted and know how you want it set up.
Ok, so I've checked the packages I used against the components I am about to buy and so I've made some modifications. I then printed the board with a laser printer just to check what's going on and I thought the pads for the ak4396 are to short for me to be able to solder the chip. So I've modified that package.
Also I've ditched the bottom ground plane, and the board is now single sided. However I now understand why so many suggested to run the power tracks on a different plane the signal lines. When tracing power tracks like I did the ground plane gets segmented and the ground paths are getting longer. However the luck is that this board is so small that I hope the ground plane will work good enough.
Other changes envolved some repositioning of the components in order to avoid shorting circuits. In the previous board I posted I've tried for example to pass a power line through the pads of a 603 ferrite bead. The printing showed me that's not going to happen.
The only problems I have left are those areas I've marked in the higher resolution image below. I don;t know how to get rid of them no matter what. If you have ideas, please advice. I couldn't set a clearance value around some individual pins, so that is not working. These are not critical but I just don't like them
Basically, if I won't discover any other problems, this goes to the fab on Monday.
Thank you all for your support! It's much appreciated.
Also I've ditched the bottom ground plane, and the board is now single sided. However I now understand why so many suggested to run the power tracks on a different plane the signal lines. When tracing power tracks like I did the ground plane gets segmented and the ground paths are getting longer. However the luck is that this board is so small that I hope the ground plane will work good enough.
Other changes envolved some repositioning of the components in order to avoid shorting circuits. In the previous board I posted I've tried for example to pass a power line through the pads of a 603 ferrite bead. The printing showed me that's not going to happen.
The only problems I have left are those areas I've marked in the higher resolution image below. I don;t know how to get rid of them no matter what. If you have ideas, please advice. I couldn't set a clearance value around some individual pins, so that is not working. These are not critical but I just don't like them
Basically, if I won't discover any other problems, this goes to the fab on Monday.
Thank you all for your support! It's much appreciated.
An externally hosted image should be here but it was not working when we last tested it.
An externally hosted image should be here but it was not working when we last tested it.
Hi,
For much better EMI I think you should remove the input data GND pin (between LRCK and CSN) and instead put a second raw of 8 GND pins at 2.54mm from the raw of input data pins (can you confirm pin space pitch 2.54mm ?).
Also beware to how your soldermask layer and clearance, correct solderresist is very important to hand solder easily (using solder paste).
Also I could be interested in 4 of these raw boards if you agree, but over here LT1763 is expensive. At what price would you supply me these boards and how much more for supplied but uninstalled LT1763s ?
usually national semi parts are much cheaper and as good as LT.
Thanks in advance
For much better EMI I think you should remove the input data GND pin (between LRCK and CSN) and instead put a second raw of 8 GND pins at 2.54mm from the raw of input data pins (can you confirm pin space pitch 2.54mm ?).
Also beware to how your soldermask layer and clearance, correct solderresist is very important to hand solder easily (using solder paste).
Also I could be interested in 4 of these raw boards if you agree, but over here LT1763 is expensive. At what price would you supply me these boards and how much more for supplied but uninstalled LT1763s ?
usually national semi parts are much cheaper and as good as LT.
Thanks in advance
see figure1 (case c=me compared to case 1=you) on page 2, for explanation on EMI loop
area (small loop is better) :
Fourni par Google Documents
area (small loop is better) :
Fourni par Google Documents
Thanks for the indications, I wasn't aware of the problem, your paper also is very informative.
I will try to place some more GND pads in that area, maybe another two, at the ends of the row, as I find it overkill to place an entire row of gnd pins in this specific application. It would mean that every signal wire (mclck, bitclck, sdata, lrclck) will arrive at the dac together with it's own gnd wire. I don't, is this something people usually do in practice?
Considering that only the first five inputs (including pdn) will be used continuously, I guess that two GND's should suffice? Then for the spi control pins, there will be a third GND.
I will come back with a drawing but the order will be the following: GND, MCLK, PDN, BCLK, SDATA, LRCLK, GND, CSN, DEM0, DEM1, GND.
The price for the 1763 is around 6.4 EUR, including VAT here in Romania. I am ordering them through Farnell. I don't intend to provide this as a kit, but if all goes well and the dac works nicely, I'll let you know what would be the cost for four boards. I can also provide you with the files, for making your own boards.
I will try to place some more GND pads in that area, maybe another two, at the ends of the row, as I find it overkill to place an entire row of gnd pins in this specific application. It would mean that every signal wire (mclck, bitclck, sdata, lrclck) will arrive at the dac together with it's own gnd wire. I don't, is this something people usually do in practice?
Considering that only the first five inputs (including pdn) will be used continuously, I guess that two GND's should suffice? Then for the spi control pins, there will be a third GND.
I will come back with a drawing but the order will be the following: GND, MCLK, PDN, BCLK, SDATA, LRCLK, GND, CSN, DEM0, DEM1, GND.
The price for the 1763 is around 6.4 EUR, including VAT here in Romania. I am ordering them through Farnell. I don't intend to provide this as a kit, but if all goes well and the dac works nicely, I'll let you know what would be the cost for four boards. I can also provide you with the files, for making your own boards.
Thank you for your input chchyong89, it's very valuable!
If I get correctly, the following are valid.
1. All the input pins in ak4396 are having internal pull-up resistors, setting them HIGH; (except 27 and 9, having pull-down resistors)
2. For getting AK4396 in parallel mode (that would be not controlling it through I2C serial bus), I need to let P/S to HIGH, that is not grounded.
3. ACKS/28 is not grounded (HIGH), and puts AK4396 in automatic mode.
4. Pin 15, goes grounded, (LOW), puts the chip in TTL mode, and the DVDD is 3.3V (CMOS requires 5V).
6. The I2S mode is controlled by DIF1, DIF2 and DIF0. For 24 bit I2S, this means dif0 is HIGH, dif1 is HIGH, dif0 is LOW. (table 11)
7. PDN pin. When grounded (LOW), the dac is in reset mode.
If I get correctly, the following are valid.
1. All the input pins in ak4396 are having internal pull-up resistors, setting them HIGH; (except 27 and 9, having pull-down resistors)
2. For getting AK4396 in parallel mode (that would be not controlling it through I2C serial bus), I need to let P/S to HIGH, that is not grounded.
3. ACKS/28 is not grounded (HIGH), and puts AK4396 in automatic mode.
4. Pin 15, goes grounded, (LOW), puts the chip in TTL mode, and the DVDD is 3.3V (CMOS requires 5V).
6. The I2S mode is controlled by DIF1, DIF2 and DIF0. For 24 bit I2S, this means dif0 is HIGH, dif1 is HIGH, dif0 is LOW. (table 11)
7. PDN pin. When grounded (LOW), the dac is in reset mode.
This also means I need to rework the board a little, I need access to DIF 1, 2, 3 for setting the I2S format with various USB interfaces. For example PCM2707 outputs 16 bits only, others, like Exa I2S USB goes up to 24 bits (32 in fact but it's not supported by 4396 anyway).
edit: also an interesting thing I've noticed since chchyong's head-up is that when in manual mode (acks grounded, LOW), the DFS pin controlling the sample rate lets the DAC work only up to 96Khz. (tables 2 and 3)
edit: also an interesting thing I've noticed since chchyong's head-up is that when in manual mode (acks grounded, LOW), the DFS pin controlling the sample rate lets the DAC work only up to 96Khz. (tables 2 and 3)
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This seems to be possible, in PCM mode the chip has five different settings: a) 16 bit LSB justified, b) 20 bit LSB justified, c) 24 bit MSB justified, d) 24 bit LSB justified and e) "24 bit I2S compatible". As I know, standard i2s has MSB transmission, and when 16bit is sent to a 24 bits DAC, the rest are simply filled with 0, or when 32 bit is sent to a 24 bit DAC, the rest is ignored. I guess mode e) is doing exactly that, then..
@chchyong89. Thanks for the recommendation, that should be useful!
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