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Old 20th March 2011, 12:24 PM   #11
SunRa is offline SunRa  Romania
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Hello,

Thank you all for your feedback, it's much appreciated.

Quote:
Hi, For someone attempting to design a pcb he should already know the
basics and as you have identified some faults you should go ahead and
redo the pcb.Asking if one should use another ground plane when you know
in electrical theory even two trace side by side will create a capacitance is
asking a silly question.
Thanks singa for your input. To be honest this is my first real attempt of designing a PCB in eagle. All the PCBs I made in the past were based solely on high-end hardware (ruler and millimetric graph paper ). And actually this is the first one to have inputs in the MHz range.

However looking at some pcb designs that were made with RF in mind, I observed that they actually employ a double ground plane, therefore I decided to do that to. On the renderings below you can't see the via's though, because I hadn't place them yet. I plan to use many of them in order to minimize any capacitance that might occur.

Quote:
Solve problems when you encounter them,then you will
learn along the way.After all this is suppose to be to be educational right? So
keep it simple and you will probably succeed.
Thanks for the advice, I try to do just that! By the way, any reason for keeping the Control Data Input Pin (DEM1 / CDTI) and Control Data Input Pin (CCLK / DEM0) connections? I plan not to make any changes in the registers and AK4396 is capable of automatically detecting the sampling rate so, any reason for keping those?

Quote:
I would also cover as much of the board as possible with ground pours, if they are tied together with vias they aint gonna cause a problem.
I would be interested in Mr Tents articles on power planes and de-coupling!
I tried to do just that regarding the ground plane. The bottom layer is mostly uninterrupted, and the top layer also has a fairly amount of ground plane.

Here is the link to Mr. Tent article.

Quote:
From recent personal experience I can say that having a ground plane directly beneath the DAC chip on the copper top was required for distortion performance.
Thanks for your reply 5th element. I did just that, both the bottom and the top graound planes are solid beneath the dac. However I just couldn't avoid using one via under the DAC for the PDN pin.

Quote:
The LT1763 need pin 1+2 tied (out+sense) together!
Thanks, I've missed that, in the next revision I will correct it!

edit: I've observed the renderings attached initially were at a low resolution so I've changed them and also connected pin 1 and 2

Followin the advice in Tent's paper, I removed the 0,1uf caps in the decoupling scheme and introduced L beads. The 10uF decoupling caps I am going to use are high quality OSCON's , with a low ESR, so no need for the small additional capacitance.
I did this for the VREF pins also. Now, there is this passage in the datasheet specifying that between VREFH and VREFL there is a 0,1uf cap. In the schematic there is another 10uF electrolytic in parallel. Any reason for the 0,1uF to be mandatory, or have any other purpose than decoupling?

I am making now the final steps for sending this to the fab so please let me know if there any further changes to be made.


Click the image to open in full size.

Click the image to open in full size.

Click the image to open in full size.


Thanks!

Last edited by SunRa; 20th March 2011 at 12:32 PM.
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Old 20th March 2011, 02:33 PM   #12
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The trace on the copper bottom that splits the ground plane pretty much straight down the middle, move this trace, unless this is by design.

You've also got a few traces on the copper bottom that really don't need to be there, unless these are by design too, move them to the copper top instead.

In the attached image you can see where I chose to route the trace that splits the ground plane in half. Only you could also do the exact same thing on the copper top instead.

I've pointed to two specific traces, but those could be on the copper top too. In fact I'd have thought you could put all the traces that are on the bottom onto the top.

Place a small resistor in series with each clock line going into the DAC, a 47R or something will be fine.
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Old 20th March 2011, 04:02 PM   #13
SunRa is offline SunRa  Romania
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Thanks for the fast reply and the additional exemplification.

I tried to keep the power lines on the bottom plane, that was the main reason for routing like that. Routing the PDN and MCLK tracks was silly indeed, I thought I can get some extra shielding though.

Here's the new version, all tracks on the top plane. The bottom plane can be a ground shield or I can scrap it. If the fab tells me that it's much less expensive to make the board without the bottom plane and all the additional vias needed to connect the two grounds then I'll just scrap it.

What do you think? Is this a release candidate?

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Old 20th March 2011, 04:24 PM   #14
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I think you need to built it and see how well it performs The board looks good.
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Old 20th March 2011, 04:34 PM   #15
SunRa is offline SunRa  Romania
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Thanks for the help and suggestions. I still have to print the circuit on a paper and check if the pads and footprints are matching. Also I'll have to arrange the silk screen a bit. Then I'll contact a fab for quotation. Having no vias, I will also considering doing it in-house, with UV method.

Regarding the control clock and control data pins, dem0 and dem1 on the board, am I right that these are not really needed? I couldn't find much info regarding this in the datasheet, just some register stuff I can hardly understand right know.
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Old 20th March 2011, 08:07 PM   #16
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On page 8 of the data sheet there is a section that describes what to do with any unused pins.
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Old 20th March 2011, 10:01 PM   #17
SunRa is offline SunRa  Romania
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Thanks, I was aware of that table and I am still trying to make my way through all the settings and configurations this DAC is able of.

However one feature I don't understand. The datasheet is continuously referring to serial and parallel mode (with PCM, not with DSD) and I couldn't find a definition regarding this. I assumed that parallel mode meant using two chips for dual mono mode but now I highly doubt it. Also I couldn't find a similar operation mode in other datasheets (for AD1955, PCM1794). Any insight on this? Are these two types of input data? I thought the I2S is pretty straightforward...
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Old 21st March 2011, 06:44 AM   #18
singa is offline singa  Singapore
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Quote:
Originally Posted by SunRa View Post
What do you think? Is this a release candidate?

Click the image to open in full size.
Hi, Not quite yet. You have laid out pcb in symetrical textbook fashion,
visually nice to look at but I feel you can shorten some traces further.
Look at both pairs of oscons don't you think their traces can be shorter?
If you rotate the angled sides towards the dac respectively you can improve the proximity of the power lines to the dac.Now you send to the pcb fab.

PS you have an orphan ground pour (pad) near pin 18 of dac.This can potentially short the smt inductor if solder overflow and cause a power short which may be costly and not easy to spot so delete it.Also check the connections to ground pour connections of other components.


singa

Last edited by singa; 21st March 2011 at 06:48 AM.
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Old 21st March 2011, 07:33 AM   #19
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Quote:
Originally Posted by SunRa View Post
Thanks, I was aware of that table and I am still trying to make my way through all the settings and configurations this DAC is able of.

However one feature I don't understand. The datasheet is continuously referring to serial and parallel mode (with PCM, not with DSD) and I couldn't find a definition regarding this. I assumed that parallel mode meant using two chips for dual mono mode but now I highly doubt it. Also I couldn't find a similar operation mode in other datasheets (for AD1955, PCM1794). Any insight on this? Are these two types of input data? I thought the I2S is pretty straightforward...
Hi SunRa,

In AKM terminology, serial means the DAC is controlled in software mode using SPI or I2C control. Parallel means the DAC is hardware controlled.

Regards
unixdeveloper
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Old 21st March 2011, 12:44 PM   #20
SunRa is offline SunRa  Romania
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Quote:
Originally Posted by unixdeveloper View Post
Hi SunRa,

In AKM terminology, serial means the DAC is controlled in software mode using SPI or I2C control. Parallel means the DAC is hardware controlled.
Thanks, would you mind developing this a bit? In parallel mode the DAC is controlled by a a combination of the pins having specific functions, while in serial mode is controlled by a microcontroller?


Quote:
If you rotate the angled sides towards the dac respectively you can improve the proximity of the power lines to the dac. Now you send to the pcb fab.
Thanks, it's a very good sugestion, I'll try it out.

Quote:
PS you have an orphan ground pour (pad) near pin 18 of dac.This can potentially short the smt inductor if solder overflow and cause a power short which may be costly and not easy to spot so delete it.Also check the connections to ground pour connections of other components.
I've noticed that too (and it's not the only occurence, there are some others around the VR's) and I wanted to address is but I don't know how to erase that portion in Eagle. It's part of the polygon making the grounding plane, and I've tried working the "isolate" and "width" value with no success. Any sugestions?
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