Build Thread - A New Take on the Classic Pass Labs D1 with an ESS Dac

all packed and ready to go, money cleared to my bank account from paypal yesterday I think, sorry I would have covered it on the card, but had a couple bills this week too. sitting here waiting for the car to get back ;( its 4.20PM, pretty sure this afternoon's last pickup is 4.30PM. will update tonight.
 
Below are the parts received from qusp today:

Coolhead - Auricap x 4, ZFoil x 1set, K-Redx1, PCB x 1, FET x 1set
atom6422- Auricap x 8, ZFoil x 1set, K-Redx2, PCB x 1, FET x 1set
ccliu - Auricap x 4, ZFoil x 1set, K-Redx1, PCB x 1,
remaining PCBx3 and FETx3 sets with nos:21, 25 & 29. According to OPC's latest list on matched FET, these nos seem not belong to any Asian members.

Please PM to confirm the quantities are correct with paypal account and shipping address. I will PM you the cost for shipping. Thanks
 
he is using Zfoils for all of the other stuff, cant remember if he got the power resistors (wasnt in teh GB). I dont know why, particularly for 30k9 as it just helps split the rails for the bias, given the tolerance will be thrown totally out of whack due to there being a pot there too I dont get it. I cant remember if you got SMD ASMP Pete, vaguely remember you didnt. The chances of finding someone with a replacement are very small, but hey who knows.
 
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opc

Member
Joined 2004
Paid Member
Hi bigpandahk,

All of that seems about right. Or at least, mine runs at those temps.

The temp of the fets depends entirely on the heatsink size, and it sounds like yours might be a little on the small side.

The regulator temps depend a lot on the voltage on the unregulated side and the voltage of the rails. They dissipate the dropped voltage.

For setup:

1. Set the output of each supply rail to the desired DC value (I use 45VDC)
2. Use the other pots to set the voltage at each DAC output node (with reference to GND) to 1.65VDC.

Allow to stabilize and re-adjust.

Once it's all stable, connect up the DAC and fire it up. Let it settle in again and adjust one last time, then you're good to go.

Cheers,
Owen
 
of course its normal to get warm, the thing is burning 50W in Class A. with such a large and long heatsink I expect it will take quite a while to reach full temp and will get hotter once you case it in. but whether its normal depends on how hot they end up in the case.

you need to carefully measure the output on the shunt regs powering AVCC on the ESS, divide that in half for AVCC/2 and note it down and set the gate bias to that with the pot with a multimeter across the source to ground.

make sure the dac is not mounted when doing the D1 setup. it is risky and also will mess with the set up voltages.

so without it fitted, set source to ground voltage on each fet to AVCC/2, wait for it to warm up, check and adjust again if needed. power down, attach dac, power it all up and adjust again as this will change it slightly. if all checks out, play some music!
 
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hey also guys, this might be useful for some of you

its from the last round, but everything is in the same places. those are M3 size dots, so 3.5mm diameter, but the numbers for the coordinates are noted in imperial. alternatively just use the cordinates in a drawing package as they are to scale.

red text is the device mounting, purple are the ackodac AKD12/8 holes in the PCB the rest are other various mounting holes on the board you can use to screw it down and pinch the fets in place
 

Attachments

  • heatsink drilling pattern.pdf
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no worries, indeed the internet is slow over here =) it takes quite a while for the signals to reach there because of the world spinning the other way in Au... ;)

dont just set to 1.65vdc, actually measure your AVCC regulator, its usually set to around 3.5v these days for the buff I think. I use 3.6v, mine is set to 1.8vdc source->ground
 
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crap, I attached the wrong pdf. sorry heres the right one, the first one above is accurate, but is the simplified version. sorry about that, it saved to another folder of the same name on my backup drive.
 

Attachments

  • NTD1 drilling pattern for forum 2 .pdf
    457.6 KB · Views: 152
no they arent, no to220 is the same as a to247, caddocks arent either. yes they do have a tab, check the datasheet for approx dimensions

you have 2 choices. drill holes for them as well and screw all the fets and resistors to the heatsink through the holes in the PCB, then and only then, solder in place (this is what I do as it assures all have good and even contact).

be careful of the zfoil legs, as they are tinned copper only, dont bend too sharp a right angle in the legs with the pliers and dont spend a lifetime wiggling the PCB to get all the fets and resistors legs through.

alternatively you can use a small piece of PCB to place between the resistor body and the heatsink to make up the gap and then use the PCB to pinch them all down, bolting the PCB down and pinching everything down at once; again dont solder till after this, otherwise you can get different heights due to tolerances.

you havent read these instructions here?
 
Owen, since first post editing is retrospective, maybe you could add these things to the first post?

Good idea! Since it is the build thread it would be nice to have the adjustment procedure on the first thread as well. I know you just posted them above but imagine if you have to search through 54 pages and more. Just makes life a lot more easier. :D

Thanks
Do
 
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Hi bigpandahk,

All of that seems about right. Or at least, mine runs at those temps.

The temp of the fets depends entirely on the heatsink size, and it sounds like yours might be a little on the small side.

The regulator temps depend a lot on the voltage on the unregulated side and the voltage of the rails. They dissipate the dropped voltage.

For setup:

1. Set the output of each supply rail to the desired DC value (I use 45VDC)
2. Use the other pots to set the voltage at each DAC output node (with reference to GND) to 1.65VDC.

Allow to stabilize and re-adjust.

Once it's all stable, connect up the DAC and fire it up. Let it settle in again and adjust one last time, then you're good to go.

Cheers,
Owen

Although I can adjust all the voltage according to the procedures, but I found that the Gate voltage for both channels are different. One channel is around 1.55V while the other is over 3.8V. I don't think it's normal. Can anyone advise what is the possible problem?
 

opc

Member
Joined 2004
Paid Member
bphk:

Are you measuring directly on the gate of the fet, or before the 220 ohm gate stop resistor? If you're measuring directly on the fet gate, then you're probing a very sensitive node and could be inducing some oscillation.

Try measuring prior to the resistor.

If all the other voltages are alright, then you should be fine, but you are correct, the gate voltage should be nearly identical for all four fets given how closely everything was matched.

Other possibilities / things to check:

-Are all your insulators to the heatsinks alright? Any shorts from the fets to the sink?

-Do you have the correct gate resistors soldered in? Are they all 220 ohm?

-Did one of the fets suffer an ESD event? This could damage but not destroy the gate and cause what you're seeing.

- Are all other voltages exactly the same between the other channels, and the good fet in the same channel?

Regards,
Owen