Hi Russ,
Yes its been a while, I have been very busy on an interesting project that compliments the Sabre DAC. Anyways, I have just realized I made a dumb mistake. The demo was performed with the SPDIF input and the DPLL_BANDWIDTH set to be Med-High. As you pointed out, you noticed differences when setting the DPLL_BANDWIDTH from low to high when running the SPDIF input. This is obviously expected by design that the performance will get worse as to set the bandwidth higher and higher, since the jitter attenuation is reduced as you open up the DPLL as it were. I guess the question is, when you did your listening test on when tinkering with the DPLL_BANDWIDTH, did you notice the low frequency showing any issues when opening up the DPLL in order to get a faster lock, or was it more soundstage accuracy being affected?
Dustin
PS.
Running the Sabre into 0V potential is perfectly fine from the circuit point of view, and matematically should offer no difference. However, when bulding the refference designs, we noticed the best THD+N results where obtained with using 1.65 (AVCC/2) as the virtual ground potential for the I/V. That being said, it was the difference between -117dB and -115dB. So maybes its a non-issue.
By the way, I have the Buffalo setup and I really like your implementation. Now I just need to find spare time to put it in a box and get some cool blue LED's on the front panel since we both know that is the key to it sounding good. JJ
Yes its been a while, I have been very busy on an interesting project that compliments the Sabre DAC. Anyways, I have just realized I made a dumb mistake. The demo was performed with the SPDIF input and the DPLL_BANDWIDTH set to be Med-High. As you pointed out, you noticed differences when setting the DPLL_BANDWIDTH from low to high when running the SPDIF input. This is obviously expected by design that the performance will get worse as to set the bandwidth higher and higher, since the jitter attenuation is reduced as you open up the DPLL as it were. I guess the question is, when you did your listening test on when tinkering with the DPLL_BANDWIDTH, did you notice the low frequency showing any issues when opening up the DPLL in order to get a faster lock, or was it more soundstage accuracy being affected?
Dustin
PS.
Running the Sabre into 0V potential is perfectly fine from the circuit point of view, and matematically should offer no difference. However, when bulding the refference designs, we noticed the best THD+N results where obtained with using 1.65 (AVCC/2) as the virtual ground potential for the I/V. That being said, it was the difference between -117dB and -115dB. So maybes its a non-issue.
By the way, I have the Buffalo setup and I really like your implementation. Now I just need to find spare time to put it in a box and get some cool blue LED's on the front panel since we both know that is the key to it sounding good. JJ
dusfor99 said:
Thanks Dustin, I would not have been able to pull it off without your excellent support.
I have found that I can here some subtle loss of fidelity about MEDIUM_HIGH BW. And yes, I would say the bass becomes a bit more muddy, but its very subtle. It really does not start to show up until you hit the "HIGH" bandwidth setting. At least that's my experience/perception. Even then its certainly not bad.
I have not had to move mine off the "LOWEST" setting for any of my sources. The only time I notice any lock issues is for the first few seconds if I cycle the power, but its not like people are going to sit there and just flip the switch back and forth while listening to the DAC.
Once mine is locked it stays locked.Cheers!
Russ
Highs and Lows
It's context/implementation sensitive.
I found that the Wolfson 8804 feeding the Sabre had nice smooth highs, almost too soft, but horrible, indistinct bass and low end. Poor solidity or foundation. No PRAT. It may be that the 8804 does something in the time domain that is just the wrong time constant for the Sabre.
However, with the TI 2707 USB 2.0 or a toslink spdif feeding the Sabre, entirely different. Some of the best phrasing, PRAT, solidity, foundation I've heard. Nice bottom, as they say. Surprisingly so from toslink, as I've been quite prejudiced against spdif since forever.
I preferred the soft/slow filter setting, have not yet heard with 9 bits.
Hey, while we have your attention a few questions for Dustin:
On the eval board (and Buffalo) the analog supplies are derived from and track the digital supply. Must this be so? Would there be any issues with separate analog and digital supplies?
To the degree that you can discuss internals: what load would result in the minimal thermal swings of the output stage? Is there a close enough load line for constant average power dissipation within the chip?
Would you consider a mono input mode some rev later? You could sense if the ratio of bclk to l/r wordclock is more or less than 32. Less than is mono, more than is stereo. This would allow zero glue interfaces with some DFs, particularly the venerable PMD-100.
And, if the internal clock feeds are differential, how feasable would an optional pecl clock input be, also for future revs? If not, never mind...
Cheers,
WMS
It's context/implementation sensitive.
I found that the Wolfson 8804 feeding the Sabre had nice smooth highs, almost too soft, but horrible, indistinct bass and low end. Poor solidity or foundation. No PRAT. It may be that the 8804 does something in the time domain that is just the wrong time constant for the Sabre.
However, with the TI 2707 USB 2.0 or a toslink spdif feeding the Sabre, entirely different. Some of the best phrasing, PRAT, solidity, foundation I've heard. Nice bottom, as they say. Surprisingly so from toslink, as I've been quite prejudiced against spdif since forever.
I preferred the soft/slow filter setting, have not yet heard with 9 bits.
Hey, while we have your attention a few questions for Dustin:
On the eval board (and Buffalo) the analog supplies are derived from and track the digital supply. Must this be so? Would there be any issues with separate analog and digital supplies?
To the degree that you can discuss internals: what load would result in the minimal thermal swings of the output stage? Is there a close enough load line for constant average power dissipation within the chip?
Would you consider a mono input mode some rev later? You could sense if the ratio of bclk to l/r wordclock is more or less than 32. Less than is mono, more than is stereo. This would allow zero glue interfaces with some DFs, particularly the venerable PMD-100.
And, if the internal clock feeds are differential, how feasable would an optional pecl clock input be, also for future revs? If not, never mind...
Cheers,
WMS
Hi Russ,
Ok that gives me confidence that it may even be just as simple as the setting of the DPLL_BADWIDTH. If not, I will have to look deeper. What I should do is actually demo both the refference design and the Buffalo next time. Time just gets hard to come by, I dont know where you get all yours. Perahps you can share the secret?
Dustin
Ok that gives me confidence that it may even be just as simple as the setting of the DPLL_BADWIDTH. If not, I will have to look deeper. What I should do is actually demo both the refference design and the Buffalo next time. Time just gets hard to come by, I dont know where you get all yours. Perahps you can share the secret?
Dustin
Re: Highs and Lows
HI WMS,
There is no need to have the analog supply be derived from the digital one, its simply that a "larger" customer wanted to see what we could do about reducing some costs without totally killing the DAC, this "customer" was our marketing deprtment. It is that simple. In ultra High end, I would think that they would be seprated.
For thermal swings, the best you can do is nail the output of the chip to a fixed potential of AVCC/2 this will cause the analog section to consume a current independent of the output level. I know it sounds like a blow off answer, but I think that the best I can do for now.
Very interesting idea you have on the bck/lr clock ratio's this would be very simple to do, so I think I will throw somthing to this effect in once a future REV is thrown at me. Thanks for the good idea.
For the differential clock inputs, I will talk with the marketing group and see. I have a feeling that since the clock inputs are part of the IO pads and chaing the IO pads can sometimes burn you (ESD/latchup....) they may likely not what to take the risk. But I will bring it up when the time comes.
wildmonkeysects said:
HI WMS,
There is no need to have the analog supply be derived from the digital one, its simply that a "larger" customer wanted to see what we could do about reducing some costs without totally killing the DAC, this "customer" was our marketing deprtment. It is that simple. In ultra High end, I would think that they would be seprated.
For thermal swings, the best you can do is nail the output of the chip to a fixed potential of AVCC/2 this will cause the analog section to consume a current independent of the output level. I know it sounds like a blow off answer, but I think that the best I can do for now.
Very interesting idea you have on the bck/lr clock ratio's this would be very simple to do, so I think I will throw somthing to this effect in once a future REV is thrown at me.
Thanks for the good idea.For the differential clock inputs, I will talk with the marketing group and see. I have a feeling that since the clock inputs are part of the IO pads and chaing the IO pads can sometimes burn you (ESD/latchup....) they may likely not what to take the risk. But I will bring it up when the time comes.
Hey Dustin:
Yer velcome.
Doh, that makes sense for my question about thermal equilibrium...when held at VCC/2 each leg will pull or push the same current, resulting in a nearly constant internal power. And with careful matching down to the parasitics in the layout as you mentioned, quadding and interleaving devices I presume, the internal thermal settling issues could likely be minimal. Terry said that a while back in so many words, but I blinked and missed it.
So as you mentioned: voltage out for parts cost, and current out held at VCC/2 for performance.
Cheers,
WMS
Yer velcome.
Doh, that makes sense for my question about thermal equilibrium...when held at VCC/2 each leg will pull or push the same current, resulting in a nearly constant internal power. And with careful matching down to the parasitics in the layout as you mentioned, quadding and interleaving devices I presume, the internal thermal settling issues could likely be minimal. Terry said that a while back in so many words, but I blinked and missed it.
So as you mentioned: voltage out for parts cost, and current out held at VCC/2 for performance.
Cheers,
WMS
Re: Highs and Lows
Hi,
I intended to use the Sabre with SPDIF receivers, in fact 4 Wolfson 8804 to start with (quickly and cheaply made), then a TC Dice.
You say it sounds horrible?
I don't really get it: shouldn't Wolfsons receive SPDIF and just retransmit the matching i2s, with some - theoretically- reduced jitter (that should end up almost cancelled by Sabre's jitter reduction)?
It's really strange, as someone else around here pointed that he got the best results... With a 8804 hooked to it.
wildmonkeysects said:
Hi,
I intended to use the Sabre with SPDIF receivers, in fact 4 Wolfson 8804 to start with (quickly and cheaply made), then a TC Dice.
You say it sounds horrible?
I don't really get it: shouldn't Wolfsons receive SPDIF and just retransmit the matching i2s, with some - theoretically- reduced jitter (that should end up almost cancelled by Sabre's jitter reduction)?
It's really strange, as someone else around here pointed that he got the best results... With a 8804 hooked to it.
Hi Dustin,
The muddy low end on the demo board is from jitter. Replace the crystal with a low jitter clock and set the DPLL to low. Then the bass is excellent.
My PCB design for my ES9008 is complete and I have ordered 3 prototype boards. Now I just have to find the time to build and test it.
The muddy low end on the demo board is from jitter. Replace the crystal with a low jitter clock and set the DPLL to low. Then the bass is excellent.
My PCB design for my ES9008 is complete and I have ordered 3 prototype boards. Now I just have to find the time to build and test it.
Like Ross and others, I have nothing bad to say about WM8804/5 or even the CS8416.
Actually every I2S source I have tried has worked very well into the Sabre chip.
There also is a the benefit that you can run the DPLL at the lowest bandwidth settings without any grief when using I2S input. This gets you the best jitter attenuation.
Cheers!
Russ
Actually every I2S source I have tried has worked very well into the Sabre chip.
There also is a the benefit that you can run the DPLL at the lowest bandwidth settings without any grief when using I2S input. This gets you the best jitter attenuation.
Cheers!
Russ
Dustin,dusfor99 said:
Well since you have measured the Buffalo/IVY combo and we now know it is capable of -117db THD, which is as good as your example. So I am relieved.
I think its a safe bet that at least for the IVY it seems to be a non-issue. Still I am trying out some theories though.
I have tried setting the common mode voltage to AVCC/2 and I can't hear any difference at all.
Still for the new discrete I/V circuit I am working on I will integrate the option to lift the common mode input to AVCC/2.
The reason I want to do it there is, that while the IVY has super symmetric feedback which may be canceling the increase in distortion you saw, the zero feedback design will of course not , so I will want to take every possible precaution.
Cheers!
Russ
Dustin,
I sent you an email about this yesterday. But maybe you are looking at this more often.
I finished up my DAC Module board for my Crimson yesterday....
My question is as follows...
I basically have 4 discrete ultra low noise regulators. Two 3.3v and Two 1.2v units, one set for analog and one set for digital. Is there any specification for the deviation between say the analog 1.2/3.3v and the digital 1.2/3.3v?
I can easily put a 20 turn pot on the analog and adjust them if needed.
BTW guys I am getting better than 128dB SN on the example board using the Prism dScope III and the USB interface.
Thanks
Gordon
I sent you an email about this yesterday. But maybe you are looking at this more often.
I finished up my DAC Module board for my Crimson yesterday....
My question is as follows...
I basically have 4 discrete ultra low noise regulators. Two 3.3v and Two 1.2v units, one set for analog and one set for digital. Is there any specification for the deviation between say the analog 1.2/3.3v and the digital 1.2/3.3v?
I can easily put a 20 turn pot on the analog and adjust them if needed.
BTW guys I am getting better than 128dB SN on the example board using the Prism dScope III and the USB interface.
Thanks
Gordon
Chillin and rhythm
Dustin:
Continuing on the theme of marketing wanting a minimal parts solution: do remind them of the importance of a hardware or standalone mode. Minimal functions, such as 6/9 bit modulator, hard/soft filter, DPLL BW, automute on/off, would be good. Also i2s/spdif, especially with mono/stereo auto detect for i2s.
rossl et al:
Aha:
The flabby bottom, lack of timing/phrasing I'm hearing is with the 8804 stock 12 MHz xtal feeding Sabre.
I was calling it the caucasian filter as it was missing rhythm, thought it might be from two servo loops being the wrong time/freq for each other, so that the combined system never quite settles down.
Thinking how good Sabre's jitter rejection is, I forgot how badly internal xtal oscs can muck things up...will try a separate regged osc for the 8804.
Cheers,
WMS
Dustin:
Continuing on the theme of marketing wanting a minimal parts solution: do remind them of the importance of a hardware or standalone mode. Minimal functions, such as 6/9 bit modulator, hard/soft filter, DPLL BW, automute on/off, would be good. Also i2s/spdif, especially with mono/stereo auto detect for i2s.
rossl et al:
Aha:
The flabby bottom, lack of timing/phrasing I'm hearing is with the 8804 stock 12 MHz xtal feeding Sabre.
I was calling it the caucasian filter as it was missing rhythm, thought it might be from two servo loops being the wrong time/freq for each other, so that the combined system never quite settles down.
Thinking how good Sabre's jitter rejection is, I forgot how badly internal xtal oscs can muck things up...will try a separate regged osc for the 8804.
Cheers,
WMS
Wavelength said:
Hi Gordon,
The power supplies are truly indpendent inside the chip so there is no wrries about having slightly different levels. As long as you dont put 3.3 on 1.2 and 1.2 on 3.3 you really should worry about even 20% deviations.
BTW, what DNR A-weighted are you getting?
Thanks
Dustin