rossl said:It works for single mono. Not dual mono.
Only listen to one channel and discard the other completely?
It looks like the author fixed it with a delay in a crossover processor after this split circuit.
I actually regard you and your experience very highly, so I will trust your experienced review. It's probably not the best circuit on the thread anyway.
More important was just highlighting the thread. I probably would choose one the simpler circuits . That is if I needed one.
Cheers!
Russ
Gee thanks, Russ
Maybe I didn't do a very good job of explaining the problem.
The I2S stereo data stream consists of a frame every sample period. For 44.1K sample rate on Redbook CDs, that is a frame about every 22.6 microsecond.
The frame has the right channel data first and then the left in serial format.
Dustin's Sabre DAC chip knows the right and left channel should be sent to the analog stage at the same time, so he has an internal delay on the right channel until the left has arrived. That delay is 1/2 sample, or about 11.3 microseconds at 44.1K.
If a designer were to split the left and right channel prior to sending mono data streams to two Sabre DAC chips, that designer needs to take account of the 1/2 sample delay needed for the right channel... The DAC chips have no way of "knowing" the timing of the other twin DAC chip, so careful design of clocks and data streams will be necessary.
Peufeu is right, it is probably best implemented in a CPLD where clocking and buffering can be better controlled.
It sounds to me like a lot of effort with not much to gain for it.
Maybe I didn't do a very good job of explaining the problem.
The I2S stereo data stream consists of a frame every sample period. For 44.1K sample rate on Redbook CDs, that is a frame about every 22.6 microsecond.
The frame has the right channel data first and then the left in serial format.
Dustin's Sabre DAC chip knows the right and left channel should be sent to the analog stage at the same time, so he has an internal delay on the right channel until the left has arrived. That delay is 1/2 sample, or about 11.3 microseconds at 44.1K.
If a designer were to split the left and right channel prior to sending mono data streams to two Sabre DAC chips, that designer needs to take account of the 1/2 sample delay needed for the right channel... The DAC chips have no way of "knowing" the timing of the other twin DAC chip, so careful design of clocks and data streams will be necessary.
Peufeu is right, it is probably best implemented in a CPLD where clocking and buffering can be better controlled.
It sounds to me like a lot of effort with not much to gain for it.
rossl said:Gee thanks, Russ
Maybe I didn't do a very good job of explaining the problem.
Your welcome.
I actually understood very well the problem you stated.
Its just I had not studied the circuit well enough to know if it actually exhibited it or why.
Still it was a good explanation.I wonder if this circuit is similarly flawed?
http://www.pedjarogic.com/1541a/I2Sbal_split.htm
Cheers!
Russ
If a designer were to split the left and right channel prior to sending mono data streams to two Sabre DAC chips, that designer needs to take account of the 1/2 sample delay needed for the right channel... The DAC chips have no way of "knowing" the timing of the other twin DAC chip, so careful design of clocks and data streams will be necessary.
Peufeu is right, it is probably best implemented in a CPLD where clocking and buffering can be better controlled.
Actually I suggested a CPLD because it's a lot simpler. Who is still going to put like 10 74HC chips in a design ?
As for the delay, you can fix it by moving one of the speakers about 3.85 mm towards you. In other words, who gives a sh*t.
Russ White said:
Your welcome.
I actually understood very well the problem you stated.
Its just I had not studied the circuit well enough to know if it actually exhibited it or why.
I wonder if this circuit is similarly flawed?
http://www.pedjarogic.com/1541a/I2Sbal_split.htm
Cheers!
Russ
Also made something similar with a 4517, also works (described here somewhere). But for all designs using this chip: if it's a HEF4517, so the old cmos stuff, it only works for i2s without oversampling. Otherwise it's too fast for this chip! Tried several and only a philips chip worked (already outside spec i2s clock >5MHz).
Otherwise it's back to many 8bit shift registers or indeed a cpld (saw one on a chinese site one day).
Guido
OK now... suppose I want 3-way active, if I use 2 Sabre DACs, say
- 1 in Stereo mode (4 DACs per channel)
- 1 with 1 DAC per channel per the woofer and 3 DACs per channel for the other driver
Would that make a difference from using 3 DACs... (probably not) and should the midrange be connected to the one with 3 or 4 DACs ?.. hm.
- 1 in Stereo mode (4 DACs per channel)
- 1 with 1 DAC per channel per the woofer and 3 DACs per channel for the other driver
Would that make a difference from using 3 DACs... (probably not) and should the midrange be connected to the one with 3 or 4 DACs ?.. hm.
For people waiting for my boards:
My computer crashed. I could save a copy of the files... but they were corrupted. No way to open them anymore.
So I just had to start again. I'm really thinking hard on the best bypass stuff, what will be assumed by the power regulator, and how to manage to get impedance notches right where I want them, for the DAC, regulators, and IV.
I'm really hesitating between 2-layers and 4-layers, because 2 layers would do the trick, but I'm wondering if 4-layers wouldn't be better - it's easier, but more expensive. I avoid too many lines crossing, but as the current flows back under the traces, i fear of getting trouble on traces on lower layers.
Tdemol told me that I should go with 2 layers and I think I'll follow his advice. Thierry, I'm ok to send you my designs - just was very busy, recording in studios this week (and next week). I'm on both sides of audio xD!.
Peufeu: No, I didn't disapeared. Just had a lot of work.
I hope I will have finished it next weekend, and will start to take orders.
Cheers,
Nicolas
My computer crashed. I could save a copy of the files... but they were corrupted. No way to open them anymore.
So I just had to start again. I'm really thinking hard on the best bypass stuff, what will be assumed by the power regulator, and how to manage to get impedance notches right where I want them, for the DAC, regulators, and IV.
I'm really hesitating between 2-layers and 4-layers, because 2 layers would do the trick, but I'm wondering if 4-layers wouldn't be better - it's easier, but more expensive. I avoid too many lines crossing, but as the current flows back under the traces, i fear of getting trouble on traces on lower layers.
Tdemol told me that I should go with 2 layers and I think I'll follow his advice. Thierry, I'm ok to send you my designs - just was very busy, recording in studios this week (and next week). I'm on both sides of audio xD!.
Peufeu: No, I didn't disapeared. Just had a lot of work.
I hope I will have finished it next weekend, and will start to take orders.
Cheers,
Nicolas
NeoY2k said:
Well, what is the price difference between two and a four layer board? Take into account that the price of the DAC will only be marginally more with a more expensive board, since most of the cost will be elsewhere, specially in a 8 channel version.
So if it doesn't matter to much in price, the result will be better, and if it's easier to design, I guess, a four layer board is not such a bad idea
That's always the case obviously, but that's not the point. It's all about price difference! Since there are going to be several boards for PSU, DAC and output (at least, that was the idea last time), you could only make parts that benefit the most of a 4-layer design, als leave the rest two layer.
So I would say: if it's not that much more expensive, and easier to design: do it!
So I would say: if it's not that much more expensive, and easier to design: do it!