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Old 10th June 2013, 07:58 PM   #2251
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New schematic attached. Now there are 64 one bit DAC:s. I do not know much about the internals of a DAC, so I think there is still somethign missing in my schematic. This schematic cannto give out music, or?


Quote:
Originally Posted by Bunpei View Post
Yes, I think your understanding is correct.



I'm not sure whether the schematic can explain the DC offset, AVCC/2 or not.
Any improvements on the schematic by audiences are appreciated.
Attached Images
File Type: gif ESS9018 Output stage-2.gif (72.3 KB, 783 views)

Last edited by staccatiss; 10th June 2013 at 08:04 PM.
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Old 13th June 2013, 12:48 AM   #2252
Bunpei is offline Bunpei  Japan
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Default Play with "No bandwidth" on DPLL setting

A Japanese manufacturer, "SFORZATO Corporation" will release a network player product, DSP-03, this month.
SFORZATO_DST_Detail (in Japanese)

They use ES9018 chips and they say that a play with a DPLL parameter "No bandwidth" is achieved in the player. Bunpei asked the developer what a mechanism has made it possible. His brief answer was;
"A reclocking of I2S/DSD signals with a synchronous MCLK just before the inputs to the DAC chips."

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Old 14th June 2013, 02:51 AM   #2253
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If they REALLY have archived no_dpll_bandwidth stable without dropouts,

distributing/reclocking differential signal (ECL?) might be a key to no_bandwidth_stability, - that should be what no one have tried before -
Just an assumption.
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Old 14th June 2013, 03:04 AM   #2254
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It works because they are clocking it synchronously and the ASRC does not really function.
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Old 14th June 2013, 12:37 PM   #2255
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I think ideal synchronous clocking should not allow varying DPLL counter value, but It's very challenging.

Narrowing DPLL Bandwidth settings make DPLL counter value variation smaller even when MCLK is synchronous, and the value never varies at No bandwidth setting.
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Old 16th June 2013, 07:47 PM   #2256
qusp is offline qusp  Australia
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I dont believe them, it doesnt work with fifo, which is synchronous and VERY low jitter, but my understanding is that the DPLL setting is meaningless with sync mode clocking anyway, as the DPLL should be doing nothing, so whats the point? Dustin himself has mentioned that in sync mode the DPLL is 'freewheeling' so sorry I think this is marketing spin. even if it is true, it doesnt mean anything, truly synchronous operation would not need the DPLL of any bandwidth.
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Old 16th June 2013, 07:59 PM   #2257
qusp is offline qusp  Australia
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Quote:
Originally Posted by wktk_smile View Post
If they REALLY have archived no_dpll_bandwidth stable without dropouts,

distributing/reclocking differential signal (ECL?) might be a key to no_bandwidth_stability, - that should be what no one have tried before -
Just an assumption.
I will try with NDK ECL in a few weeks again just to be sure, but I think this is purely academic
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Old 28th June 2013, 02:10 PM   #2258
Bunpei is offline Bunpei  Japan
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Default ES9018-2M Sabre32 Reference Stereo DAC

Has anyone obtained a datasheet of this new model?

http://www.esstech.com/Pr_2013/ES901...R%20130621.pdf
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Old 28th June 2013, 03:09 PM   #2259
Shinja is offline Shinja  Japan
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looks sweet.
I thought the load current of IV opamp is too heavy at stereo or mono mode of ES9018.
ES9018-2M seems the spin off of 2ch from ES9018.
However it is a pity that its DNR is worse than ES9018's 8ch mode.
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Old 28th June 2013, 03:35 PM   #2260
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Hi guys,
I am an ES9018 fans and a DSD lover. I saw a video from ESS Sale Office(China) recently, Mr. Zhang said that the 9018 isn't 1bit DSD DAC chip, and DSD to PCM conversion will be done in 9108(i disbelieve it, maybe a big confusion?).

I got other opposite informations from computeraudiophile.com about this. Mr. Michal who is the designer of Mytek, here are his words:
"Ok,the way DSD is implemented in our DAC:
DSD 1 bit> digital DSD 3 pole filter @ selectable 50,60 or 70kHz>6 bit output > 6 bit DAC. The filter, standard in all sacd players (typically analog) helps to filter out of band noise inherent n DSD. Such filtering requires multiplication which produces result in more bits than the 1bit input. It's actually in away better than 1 bit because all info is preserved but 6 bit conversion is more accurate than 1 bit. It's better to keep it at 6 bits than round it to 1 bit, for example. We are still talking about 64xFS stream of 6 bit data , NOT any PCM."

According to Mr. Michal's descriptions, the ES9018 does 6-bit SDM and the DSD SR is still 2.8M(or 5.6M), No any PCM.

Who is right?

Thanks!
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