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Old 6th December 2011, 04:28 PM   #1891
Bunpei is offline Bunpei  Japan
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Default Questions on the Effect of Oversampling Filter of DSD input

According to "FUNCTIONAL BLOCK DIAGRAM" in data sheet of ES9018, DSD signal is processed in "OVERSAMPLING FILTER" block.

1. My interpretation is "no oversampling is applied to DSD data signals in this block".
Do you think it is correct?

2. In the case of I2S input, "OSF=ON or OFF" affects the effective magnitude of DPLL Bandwidth parameter. Even in the case of DSD input, does the setting "OSF=ON or OFF" affect the DPLL behavior?
As for a clock to which DPLL is subject, BCLK is said to be selected for I2S. How is for DSD? Is BCLK of DSD used for DPLL input?
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Old 23rd December 2011, 02:57 AM   #1892
Bunpei is offline Bunpei  Japan
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Default DSD256 play on ES9018

Chiaki achieved a successful play of DSD256 sources on ES9018 implemented on Japanese Fidelix CAPRICE DAC. The transport used was Chiaki's SDTrans384 with Sync option. Oversampling mode was ON and DPLL Bandwidth Parameter was the "LOWEST". A synchronous master clock of 90.3168 MHz was employed.
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Old 23rd December 2011, 11:28 AM   #1893
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Do you mean DSD 256fs? Does it exist? Was ES9018 in phase mode?
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Old 23rd December 2011, 11:53 AM   #1894
Bunpei is offline Bunpei  Japan
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Yes, its DCLK frequency is 44.1 kHz x 256 = 11.2896 MHz.

The DSD256 file was not prepared by any actual recording. I created it based on the method shown by flemming3520;
exaU2I - Multi-Channel Asynchronous USB to I2S Interface

The D1 and D2 signals given to ES9018 are of "DSD Normal mode".
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Old 8th January 2012, 02:47 AM   #1895
glt is offline glt  United States
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Hi Bunpei,

I've tried OSF bypass with 80MHz clock.

- It only works if the incoming sample is 384KHz.
- Any less and the dpll cannot lock when music is playing. It locks when there is no music playing.
- The value of the dpll is /64 (I was expecting /8)

Are there any other register to adjust when using the OSF bypass?

Thanks...
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Old 8th January 2012, 12:54 PM   #1896
Bunpei is offline Bunpei  Japan
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Quote:
Originally Posted by glt View Post
I've tried OSF bypass with 80MHz clock.

- It only works if the incoming sample is 384KHz.
- Any less and the dpll cannot lock when music is playing. It locks when there is no music playing.
- The value of the dpll is /64 (I was expecting /8)

Are there any other register to adjust when using the OSF bypass?
Hi, glt!

To my regret, I have no experience of playing 384kHz/32bit PCM on 80MHz ES9018.
The behavior seems very strange for me.
I think no other register setting is required for an OSF bypass.

Bunpei
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Old 12th January 2012, 01:51 PM   #1897
perra_e is offline perra_e  Sweden
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Quote:
Originally Posted by Russ White View Post
Since I have received a few emails asking how its done here is how you get DSD from any SACD player which uses the PCM1791 like the Denon DVD-2910.

Pin 1 is DATA R
Pin 3 is DATA L
Pin 5 is the bit clock.
Then you just need GND.

Cheers!
Russ
I found this old description of how to get the DSD from a Denon DVD-2910. I just wonder if any one knows if all tone controles, incluing volume, are bypassed when selecting "source direct" in the player so the pure DSD stream is captured when picking it from the DAC.

--Per
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Old 21st February 2012, 11:57 PM   #1898
Bunpei is offline Bunpei  Japan
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I found Dustin's name here
DSD via USB, Toward An Open Standard | AudioStream
with his company name, "Independent".
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Old 26th February 2012, 03:28 PM   #1899
Bunpei is offline Bunpei  Japan
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Default Is a latch mechanism available for a read-out of DPLL_NUM?

Some ES9018 users including Hifiduino users may read 32 bit DPLL_NUM value through a series of four byte-by-byte access to register #28,#29, #30 & #31 via I2C. No latching method of the four register values is shown in ES9018 datasheet.
Does anyone know whether a latching mechanism is provided or not?

Without such a latch, we can not read an exact value of DPLL_NUM in some typical cases.
For example, in the case of applying a synchronous MCLK of 90.3168MHz, DATA_CLK of 2.8224MHz is represented as the value 0x08000000 in DPLL_NUM. However, in actual situations, it fluctuates to some extent, for example, 0x07FFFFFF – 0×08000001. While we read out register #28 – #31 values one by one, the whole value changes and each byte changes. In the worst case, an obtained value of DPLL_NUM indicates 0x08FFFFFF or 0x07000000. (We usually get a result of random shuffles.)
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Old 26th February 2012, 03:49 PM   #1900
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Quote:
Originally Posted by perra_e View Post
I found this old description of how to get the DSD from a Denon DVD-2910. I just wonder if any one knows if all tone controles, incluing volume, are bypassed when selecting "source direct" in the player so the pure DSD stream is captured when picking it from the DAC.

--Per
Denon says that in Source Direct (50kHz or 100kHz filter), the DSD stream goes unaffected into the DAC inputs. The filters are actually analog filters inside the DAC, so they won't affect the DSD stream. Selection is done with some 74LVC157 - easy to check (DSD_SEL). Same system is inside DVD-2930 too.
Attached Images
File Type: jpg dvd-2910_DSD2.JPG (83.0 KB, 496 views)

Last edited by SoNic_real_one; 26th February 2012 at 04:09 PM.
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