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#1891 |
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diyAudio Member
Join Date: Aug 2008
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According to "FUNCTIONAL BLOCK DIAGRAM" in data sheet of ES9018, DSD signal is processed in "OVERSAMPLING FILTER" block.
1. My interpretation is "no oversampling is applied to DSD data signals in this block". Do you think it is correct? 2. In the case of I2S input, "OSF=ON or OFF" affects the effective magnitude of DPLL Bandwidth parameter. Even in the case of DSD input, does the setting "OSF=ON or OFF" affect the DPLL behavior? As for a clock to which DPLL is subject, BCLK is said to be selected for I2S. How is for DSD? Is BCLK of DSD used for DPLL input? |
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#1892 |
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diyAudio Member
Join Date: Aug 2008
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Chiaki achieved a successful play of DSD256 sources on ES9018 implemented on Japanese Fidelix CAPRICE DAC. The transport used was Chiaki's SDTrans384 with Sync option. Oversampling mode was ON and DPLL Bandwidth Parameter was the "LOWEST". A synchronous master clock of 90.3168 MHz was employed.
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#1893 |
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diyAudio Member
Join Date: Jul 2008
Location: Lviv
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Do you mean DSD 256fs? Does it exist? Was ES9018 in phase mode?
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If for pristine and pure adoration - it's diyAudio dedication! |
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#1894 |
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diyAudio Member
Join Date: Aug 2008
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Yes, its DCLK frequency is 44.1 kHz x 256 = 11.2896 MHz.
The DSD256 file was not prepared by any actual recording. I created it based on the method shown by flemming3520; exaU2I - Multi-Channel Asynchronous USB to I2S Interface The D1 and D2 signals given to ES9018 are of "DSD Normal mode". |
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#1895 |
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diyAudio Member
Join Date: Oct 2004
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Hi Bunpei,
I've tried OSF bypass with 80MHz clock. - It only works if the incoming sample is 384KHz. - Any less and the dpll cannot lock when music is playing. It locks when there is no music playing. - The value of the dpll is /64 (I was expecting /8) Are there any other register to adjust when using the OSF bypass? Thanks...
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www.hifiduino.wordpress.com |
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#1896 | |
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diyAudio Member
Join Date: Aug 2008
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Quote:
To my regret, I have no experience of playing 384kHz/32bit PCM on 80MHz ES9018. The behavior seems very strange for me. I think no other register setting is required for an OSF bypass. Bunpei |
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#1897 | |
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diyAudio Member
Join Date: Mar 2004
Location: Jönköping
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Quote:
--Per |
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#1898 |
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diyAudio Member
Join Date: Aug 2008
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I found Dustin's name here
DSD via USB, Toward An Open Standard | AudioStream with his company name, "Independent". |
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#1899 |
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diyAudio Member
Join Date: Aug 2008
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Some ES9018 users including Hifiduino users may read 32 bit DPLL_NUM value through a series of four byte-by-byte access to register #28,#29, #30 & #31 via I2C. No latching method of the four register values is shown in ES9018 datasheet.
Does anyone know whether a latching mechanism is provided or not? Without such a latch, we can not read an exact value of DPLL_NUM in some typical cases. For example, in the case of applying a synchronous MCLK of 90.3168MHz, DATA_CLK of 2.8224MHz is represented as the value 0x08000000 in DPLL_NUM. However, in actual situations, it fluctuates to some extent, for example, 0x07FFFFFF – 0×08000001. While we read out register #28 – #31 values one by one, the whole value changes and each byte changes. In the worst case, an obtained value of DPLL_NUM indicates 0x08FFFFFF or 0x07000000. (We usually get a result of random shuffles.) |
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#1900 | |
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diyAudio Member
Join Date: Jan 2008
Location: Virginia
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Quote:
Last edited by SoNic_real_one; 26th February 2012 at 03:09 PM. |
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