ESS Sabre Reference DAC (8-channel)

[Bunpei]

By using TPA Buffalo III board, we can now try one of the undocumented ES9018 register settings, Differential output mode, "True" or "Pseudo". This setting has a close relationship to Quantizer Bit Length, especially 9 bit mode.
On this topic, we can read Dustin's original post and glt's valuable report on his intensive experiments.

First, I'd like to have a clear understanding on the meaning of "True" and "Pseudo" in the differential mode and to appreciate your comments.

My basic understanding is;
1. In "True" differential mode, an normal output signal "+" appears between A_GND pin and "DACn" pin and counterpart output signal "-" appears between A_GND pin and "DACnB" pin.
2. In "Pseudo" differential mode, a single output signal appears between "DACn" pin and "DACnB" pin.

What I can't understand well is how this difference would affect the design of I/V stages, especially in terms of GND handling. In my case, as I only use transformer I/V stage or earphones and use no GND pins, no difference is recognized.

[Bunpei]

Originally Posted by Bunpei

By using TPA Buffalo III board, we can now try one of the undocumented ES9018 register settings, Differential output mode, "True" or "Pseudo". This setting has a close relationship to Quantizer Bit Length, especially 9 bit mode.
On this topic, we can read Dustin's original post and glt's valuable report on his intensive experiments.

I'd like to continue the topic especially on a consideration of quantizer bit setting. I'm not sure whether the term "quantizer" is a popular technical term in the field of sigma-delta DAC or not.
My basic understanding is as follows;

1. A sigma-delta type DAC chip consists of a "modulator" and a "digital to analog" module. The first generation sigma-delta DAC used to have 1-bit digital to analog conversion hardware.
2. In the case of this modern Sabre32 architecture, the chip has a bunch of 6 bit "digital to analog" modules in a chip. The number is 8 modules ( 4 channels x 2 (+,-) ) per side and totally 16 modules.
3. When the 9 bit quantizer setting is selected, the modulator generates time series values that match 9 bit digital to analog module. However, the hardware is of only 6 bit capability. Extra 9-6=3bit ( 0 - 7 level) is processed as the simple ON/OFF of the 8 modules of which analog outputs are set to be tied together on this setting. This can be regarded as just one digital to analog module per side. On the setting, having a true differential + and - outputs is impossible and only a pseudo differential output is available.

[Bunpei]

Chiaki made a set of optional boards for demonstrating "Proof of Concept" of effectiveness of synchronous MCLK feed to ES9018 DAC chip using dual oscillators.
(The smaller board at the top left in the picture below is a DAC side sub board and the larger one at the bottom right is a transport side sub board.)


I guess the similar scheme might be realized in the next new TPA USB-I2S board.
Two oscillators, 90.3168 MHz & 98.304 MHz, are located on the DAC side sub board. The oscillators are located on the left bottom corner of the board. They are NDK (Nippon Denpa Kogyo) low phase noise LVPECL output type devices.
(The DAC side sub board is embedded into Japanese Fidelix CAPRICE DAC.)



One of two frequencies is to be selected depending on the sampling frequency of the source by a command sent from the transport side via I2C lines on PS-Audio standard I2S interface (I2S/LVDS & I2C on HDMI Connector & Cable).
The selected oscillator output is injected to ES9018 chip and also supplied back to the transport side via HDMI cable.
(The transport is Chiaki's SDTrans384.)



On the trasport side, the 90.3186 MHz or 98.304 MHz MCLK is divided into suitable frequencies to be used. MCLK synchronized I2S signals are send to DAC via PS-Audio standard I2S interface. The LVDS signals are isolated on the DAC side board.

As a result, under this synchronous MCLKing scheme, a stable lock state even on 384 kHz/32 bit PCM I2S input to ES9018 is obtained with register settings, OSF=ON, Jitter Eliminator=ON, DPLL Bandwidth=The Lowest.

The sonic impression of output music is excellent and Bunpei think it is demonstrating a very high potential that the ES9018 DAC chip originally possesses.

[Coris]

Many thanks for the details here!

[guglielmope]

Hello Bunpei,
and now why you don't build a new ES9018 Dac board with this solution for the SDTrans384 users?
A new board made with the same philosopy of the SDTrans?
Ciao
Guglielmo

[davewantsmoore]

Originally Posted by guglielmope

Hello Bunpei,
and now why you don't build a new ES9018 Dac board with this solution for the SDTrans384 users?

Thankyou Bunpei for keeping us informed of the excellent progress.

I am following along this thread hoping that I can buy a SDTransport if a new version is ever produced.

Hopefully by that time I am also able to utilise this work in sync mclk 9018, it seems very promising.

[alanvcd]

wow, will these optional boards available for order?

[Turbon]

Originally Posted by davewantsmoore

Thankyou Bunpei for keeping us informed of the excellent progress.

I am following along this thread hoping that I can buy a SDTransport if a new version is ever produced.

Hopefully by that time I am also able to utilise this work in sync mclk 9018, it seems very promising.

Yes, I would be very happy indeed if given a chance to buy one of these!

Brgds

[Turbon]

Yes, please hurry up guys!

[Bunpei]

Dear digital audiophiles,

Chiaki and Bunpei were much pleased with the so many comments for the previous post.
As for the next release of SDTrans, would you read this post?
MicroSD Memory Card Transport Project

Chiaki and Bunpei