Little UCD help
Not to create new topic :
Classic (more or less, I changed feedback loop to get higher error suppressing ratio).
I did make UCD like long time ago using irs 20957 and it works fine for 5 years:
I wonder what will happen if there is no load (speaker disconnected). According to spice feedback loop simulation, oscillating frequnecy will be only 37 khz.
I did not try, but I presume nothing will happen to mosfets. current will be quite low.
Am I right? Have you tried ?
Now I am designing new class D using also IRS20957 but irfb4227 mosfets two in paralell per half of the half bridge.
I wonder to use or not ultra-fast diode paralel to mosfets? IRF NEVER use such diode claiming irf4227 body diode is fast enough.?!
irs20957 has OCP integrated. ir2110 and similar only have SD pin.
I will use Zetex PNP and NPN totem pole to boost current according to the irf refference desing (irs2092 has identical output section as irs 20957).
Little problem for irs20957 could be maximum dead time of 80 ns compared to 105 ns of irs 2092, but I think there should be no problem .
I will increase gate charge resistor to 8.2 ohm and discharge by 4.7ohm. IRF uses 4.7 both for charging and discharging. but has 120 ns dead time. (iraudamp 9)
Iraudamp 9 metions "click noise", and that irs2092 has click noise suppression circuit inside: Did anyone understand what does it mean:
I made irs20957 ucd before and no click noise at all, without any protections like UVP, there is just 10 uF at SD pin makes it charge slowly. Probably UCD startup does not exhibit click noise, comared to IRF sigma delta modulators (pre filter loop) ?
Regards.
Not to create new topic :
Classic (more or less, I changed feedback loop to get higher error suppressing ratio).
I did make UCD like long time ago using irs 20957 and it works fine for 5 years:
I wonder what will happen if there is no load (speaker disconnected). According to spice feedback loop simulation, oscillating frequnecy will be only 37 khz.
I did not try, but I presume nothing will happen to mosfets. current will be quite low.
Am I right? Have you tried ?
Now I am designing new class D using also IRS20957 but irfb4227 mosfets two in paralell per half of the half bridge.
I wonder to use or not ultra-fast diode paralel to mosfets? IRF NEVER use such diode claiming irf4227 body diode is fast enough.?!
irs20957 has OCP integrated. ir2110 and similar only have SD pin.
I will use Zetex PNP and NPN totem pole to boost current according to the irf refference desing (irs2092 has identical output section as irs 20957).
Little problem for irs20957 could be maximum dead time of 80 ns compared to 105 ns of irs 2092, but I think there should be no problem .
I will increase gate charge resistor to 8.2 ohm and discharge by 4.7ohm. IRF uses 4.7 both for charging and discharging. but has 120 ns dead time. (iraudamp 9)
Iraudamp 9 metions "click noise", and that irs2092 has click noise suppression circuit inside: Did anyone understand what does it mean:
I made irs20957 ucd before and no click noise at all, without any protections like UVP, there is just 10 uF at SD pin makes it charge slowly. Probably UCD startup does not exhibit click noise, comared to IRF sigma delta modulators (pre filter loop) ?
Regards.
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hi grizlek . please post your schematic and photos of your project.
by the way was there any noise issues with your project ?? how many channels did you make in one casing and what voltage did you use??
What do you mean "noise" ? input to gnd, and output level noise?
When I put ear on the 200W speaker, maybe I can hear something, but this is normal for any amplifier.
1 channel per pcb.
No photos yet, this new schematics is not yet drawn, basicly it is related to iraudamp 9, using similar output section, irs20957 is almost identical.
Comparator will be TL3016
OPA134 is first stage before comparator:
Lower the "UCD" amplification, lower the noise, and THD.
Highest the closed loop gain at audio frequencies / gain at switching frequencies ratio, lowest THD.
Comparator does not like low voltage signals at the inputs (highest errors), so: Lower the "UCD" amplification higher voltages at comparator imput, lower the noise, and THD.
Goal is to make as high as possible first stage using good op amps, to get +/- 8V max, then UCD amplification is only by 10 to fulfill +/- 80V supply.
Good op amps have 0,0001 THD at +/- 8 Vpp, (supply +/-15V) for example.
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I think he mean the interference "noise" when operating 2 amplifiers next to each other and everything neccessary is connected (inputs, GNDs).
You are talking about an unspecified schematic. Nobody can tell if you were right. Your statements are also underspecified. 37kHz? Obviously it depends on the schematic and the values. What is a "feedback loop simulation"? I know AC simulation and transient simulation for example, but no "feedback loop simulation". "low" current? how low?
That's true, diode of IRFB4227 is fast enough, and parallel diode is basically ineffective in any case, it will conduct negligible current.
This is basically correct. Maybe you could decrease both resistors, but this is not critical. Unless you want to achieve the least possible distortion. Because then you must optimize them fully.
By simply lowering gain of UCD you can not achieve higher loop gain. Gain of comparator (=PWM modulator) is determined by the ratio of power supply voltage and the switching residual voltage at the input of comparator. By setting stronger feedback you increase switching residual voltage and error voltage by the same amount, therefore you will get the same output error cancellation ratio. Only disturbances coming from other sources (like the other channel) and disturbing the comparator can be compressed this way. But basically these disturbances should be better suppressed by proper layout, filters, and maybe shielding.
P.S.: Please learn more English and electronics terminology! Quite hard to understand your sentences.
BTW: gain at switching freq is always 1, since the oscillation is stable. If not 1, then it means the modell is not appropriate at this freq, or the oscillation is not stable.
"Closed loop gain" you probably mean loop gain. Closed loop gain would be the gain of the amplifier in closed loop, but you don't think about this quantity.
If housing is metal and grounded properly noise is minimal.. more or less not related to the amplifier.
Would it be related to power supply rejection ratio in this case hmm?
Lets say then feedback loop simulation:
But for example lets presume no load amp will oscillate at between 30 kHz and 35 kHz. (it can be proven in spice all in all).
But impedance of LC filter at 35 khz for example will not produce any too significant current through mosfets. (it also can be shown in simulation) If this current is not enough to trigger OCP by IRS20957, I do not see what else bad could happen ?!
There are some ultrafast diodes rated at 25 nS. For example sure elec. use this diode: STTH1602C
Sure Electronics' webstore 1 x 2500 Watt Class D Amplifier Board - IRS2092
Correct, but by lovering UCD amplification I get higher voltages at comparator input = lower comparator error = lower thd, proven by spice simulation and real device.
Using real comparator in LTspice (real model, not just virtual model) this is not the case, comparator delay is affected by imput voltage difference, if both voltages are low output delay is affected , (as I recall, but maybe also some other parameters) .
Error cancelation ratio is the same but comparator produces more error with low input voltages !! (I do not recall have to check in spice what kind of errors is that, 5 years passed)
Real comparator can not behave identically when we have both imput voltages at 1mV range and 300 mV range , it has to affect delay, also there is comarator offest , etc..
Also there are no "disturbances" in LT spice simulations. And behaviour proves this theory . Reduce the amplifier gain reduce the thd. This is no the case with "virtual" comparator.
I did not write English regarding amplifiers long time .
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Is this your particular experience for that amp you built? Or is it a general statement for every amps based on many different built amplifiers, or you deduced it?
If this is your actual experience for your amp, then be happy with it! But if general statement, then not true.
I dont know what case do you think of, but basically no. I talk about an interference transmitted at high freq (many MHz). PSRR is not defined over switching freq.
You used more words, but no relevant information was added. Still no schematic, no part values, still no mention what you call "feedback loop simulation".
I see too much possibilities.
(I don't like trr defined in nanosiemens dimension.
)Why do you think this is the relevant parameter here? Try to calculate how much current will it conduct, and how much current left in the original MOSFET while tying them in parallel!
That is true, if comparator has its own error, then it should be used with higher voltage. But for this you don't have to alter anything in the feedback topology. You can set as high carrier amplitude on comparator input as you wish, by simply amplifying the error signal. I usually set Vcc/5... Vcc/3. No problem with comparation any more. And the error of comparator itself is an other source of disturbance in my point of view. (Other than the most important, inherent ones: dead time, nonlinearity of filter, variing fsw.)
Some components of it. Components that should not be exist if proper comparator was used. And you talked about loop gains previously, not about bad comparators.
Well, all is related to all, of course this is my statement. Especially in this case we have HF signals, etc. But how can I comment somebody else's amplifier which I have never seen.
Then how can this noise be transmitted at the amp output to be heared?
I mean how can audible noise or hum be related to HF (pwm signal) interference ?
If G(s) is LC filter, if feedback network is H(s), if delay is delta(s), then loop is:
Al(s)= G(s)*H(s)*delta(s)
Like ?
They will conduct inductor current in dead time when mosfet body diodes are not conducting due to the being slow. This may alter total THD, (have not done such simulations) and I do not claim anything.
According to simulation comparator errors are VERY significant. Doubling the comparator input voltage makes thd reduce by half (for example)
Please explain this, "high carrier amplitude" . What you use to amplify error signal.
Virtual, lets say ideal ..
Maybe, somehow. But for me it's impossible to figure out the relevance of this (quoted above) statement.
Of course. This is why nobody asked if it is yours or not.
Yes, we have HF signals. So...?
Is this a real question? If not, then what is the meaning?
I can't find your answer to my question.
On nonlinear elements amplitude modulation can be demodulated. AM is generated by superposition of 2 HF signals at almost but not exactly the same freq.
Nobody talked about hum this before. But if PWM amplitude or freq is modulated by hum, then it also can be demodulated after transmittion and mixing.
- Who asked this? What's the relevance? Where is the so called "simulation"?
- Where is the active element? Do you mean the whole active circuit is part of the feedback except for its delay? :-D Quite strange separation.
- How you determine the factors?
- How you deduct nonlinear behaviour from a linear modell?
Like anything. How could I compare many different things to a particular thing?
Forward conduction speed is never a problem in ClassD audio, they conduct almost instantly. Reverse recovery is the slow one. Trr.
I don't know what simulation you refer to.
It's easy to arrange a simulation dedicated to show only the effect of comparator error. In this case obviously higher voltage on comparator results in inversely proportional THD. But in a well designed real design comparator error is not dominant.
What to explain? I already wrote Vcc/3 (peak to peak). Should I explain what carrier means?
OPA, LTP + unbuffered inverter, it can be any kind of fast amplifier with low noise and good overload recovery behaviour. Even slow amplifiers are usable in UCD if you ensure there is no "windup".
At this moment we can consider that simulation of just passive elements, LC filter and passive feedback loop (without comparator) is in direct relation with amplifier behaviour.
Just Al(s)= G(s)*H(s)*delta(s) response to the AC sine analysis : Al at audio frequency range / Al at switching frequency is in direct relation to distorsion suppresion, this is also claimed by B. Putzeys. But of course this is NOT REAL model just one of "approximation models".
In general what op amp would you suggest to amplifie error signal ? Such op amp should be relatively very fast not to affect phase at switching frequency significantly.
.
For reverse recovery I agree completely, but all in all external STTH diode seems to be much faster Trr, how this affects THD should be seen by real model.
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OK, so do you want to say that "feedback loop simulation" means AC (small signal) simulation of the passive network? Quite long time and many effort to answer a simple question.
Yes, there is relation. And what was the relation? And how you deduced your claims from this?
How completely omitting the comparator from the modell could tell anything about specifically the errors introduced by the comparator?
No, it doesn't have to be very fast. As you must know UcD needs additional phaseshift (over the ideal modell) to reach 180 degree at practical frequency. This OPA is a perfect option to introduce the missing phase. It only have to be immune to HF interference. (High slew rate.)
OK, model it, but since almost no current will flow on it, there is no much chance to help.
Maybe if you specified which amp you talk about you would have been answered. But don't expect any answer related specifically to your speaker and music listening habits. Nor about your shielding and grounding mistakes causing hum.
There are no really rugged amps here (except for ClassA ones). All amps in diyaudio are as is, no professional tests, no worst case consideration made, you can use them only for your own risk.
Some amps have some kind of protections, but I haven't see any that is unconditionally safe.
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Well you are asking for simulations, I do not have old ones (cant find them), I plan to do the new onse, old ones are 5 years old (more or less).
All in all my goal is to make Al in such way that loop gain at audio range is much higher then loop gain at switching frequencies.
Bruno Putzeys, of course in his patent only gives basic feedgack using only RC paralel with R. But he also designed much advance feedbacks using op amps, which in the end give much lower thd.
I did some attempts in spice, 5 years ago and they just do not want to oscillate in spice, I wonder if real experiment would make any difference.
If you want to have even lower loop gain ( Al described above ) at switching freq in my case, then phase shift at 180 degree will occur even at lower frequency. goal is to prevent that.