Class D at low volume levels

[Ouroboros]

Tripath amps are defenitely NOT the self oscillating amps...

ReallY? I've just looked at the Tripath US patents 5909153, 6351184, 6549069 and 6580322 and they clearly show that the modulator is part of a self-oscillating loop. Perhaps you can show me a reference that clearly shows the special separate variable-rate clock generator.

 

[81bas]

ReallY? I've just looked at the Tripath US patents 5909153, 6351184, 6549069 and 6580322 and they clearly show that the modulator is part of a self-oscillating loop. Perhaps you can show me a reference that clearly shows the special separate variable-rate clock generator.

Variable-rate output frequency does NOT mean, that the amp is self oscillating. Sigma-delta modulator does produces a wideband output frequency also, but it is NOT an self oscillating modulator...
Also, most of these patents you called here are having references to the various patents about higher order sigma-delta modulators, does it says you about something?

And please, try to look with the oscilloscope into the square wave output of the T-amp chip, it will say you a lot about the modulation principle. A lot of datasheets of T-amps are saying about some mystical 'modulation pattern'. Usual analog self-oscillating class-D amp has NO any modulation patterns.

 

[81bas]

ReallY? I've just looked at the Tripath US patents 5909153, 6351184, 6549069 and 6580322 and they clearly show that the modulator is part of a self-oscillating loop. Perhaps you can show me a reference that clearly shows the special separate variable-rate clock generator.

Also, please look carefully into each of these patents (US5777512 also), all of them are having so called sampled comparator. It is a comparator, which holds it's output state at least one cycle of the given Fs (sampling frequency). And it does the control loop to be discrete (non-contiguous) which exactly limits the resolution of the modulator... And it is exactly the difference from the usual self-oscillating amp...

 

[theAnonymous1]

It looks as if the high time period is constant, which would effectively be pulse density modulation.

I must say that I thought the tripath amps were another self-oscillating design, with a more complex than usual feedback modulator. If they really were PDM, then a bridged version would need to use 3-level modulation. Are you really sure this is the case?

pulse-density modulation (a digital amplifier technology still used by companies like Sharp and Tripath Technologies)

It's an article about TI's Class-D efforts, but contains the above quote.....

EETimes.com - TI front-to-back digital audio chain bows

 

[phase_accurate]

Until a few years ago I also thought that Tripath's are clocked delta-sigma amps - maily due to the aforementioned patent.
OTOH the often reported idle switching frequency around 1 MHz would point to a sampling rate at around 2 Ms/s.
I don't think that the performance figures ot the Tripath amps could actually be achieved with low order D-S loops at sampling frequencies that low so I think that the commercially avaialble Tripath's are self-oscillationg. But I am open to other opinions.

With digital storage scope it shouldn't be that difficult to see whether it uses a discrete clock: All switching states should measure INTEGER multiples of the clock period if this is the case !

Regards

Charles

 

[81bas]

Theoretically it possible to achive the good results with high order sigma-delta modulator (in the patent above we see at least the second order D-S modulator) with relatively low sampling frequency. They have used also some proprietary feedback loops, making D-S modulator not so noisy...

Also, with usual oscilloscope it is very easy to distinct between _usual_ self oscillating amp and D-S modulation amp. Sure, at idle they look very similar, but with slowly alternating input voltage the D-S modulator will start to produce some typical modulation 'patterns', which will clearly show the difference...

And if the T-amp is NOT a D-S modulator amp, they do use the sampling comparator almost in all above mentioned patents. This will limit the amp resolution also...

It is possible also, that the bad sounding at low level T-amp has simply bad PS decoupling or bad PCB layout, as it was mentioned above, but who knows...

 

[theAnonymous1]

Here is some useful info I came across while searching for info on PDM.....

What’s the difference between PWM and PDM?

PWM compares the analog-audio input signal to a triangular or ramping waveform that runs at a fixed carrier frequency, creating a stream of pulses at the carrier frequency. Within each period of the carrier, the duty cycle of the PWM pulse is proportional to the amplitude of the input signal.

PDM is generally accomplished with a sigma-delta modulator. The number of pulses in a given time window is proportional to the average value of the input signal. Individual pulse widths are “quantized” to multiples of the modulator clock period.

What are the comparative advantages and disadvantages of PWM and PDM?

PWM allows 100-dB or better audioband signal-to-noise ratio (SNR) at fairly low carrier frequencies. (Lower frequencies limit switching losses.) Theoretically, PWM modulators are stable up to nearly 100% modulation, permitting high output power. Yet in practice, PWM pulse widths become very short near full modulation, challenging real-world drivers.

Much of the appeal of PDM is that a sigma-delta architecture distributes much of the high-frequency signal energy, rather than concentrating it at carrier-frequency harmonics, as in PWM. Further, although energy still exists at images of the PDM sampling clock frequency, the PDM clock frequency is typically much higher than a PWM carrier—on the order of 3 to 6 MHz. That places the sampling clock images outside the audio-frequency band.

Also, in portable devices that have multiple audio channels (main speaker/ headset, ringtone, etc.), the inherent randomization of the output modulation in PDM eliminates beating between multiple amplifiers. Finally, PDM can achieve high modulation levels because pulse widths can never be narrower than one sampling-clock period.

What has worked against the wider use of PDM to date is that conventional 1-bit modulators are only stable to 50% modulation. Additionally, at least 64-times oversampling is needed to achieve sufficient audio-band SNR, so data rates of at least 1 MHz are required, which translates to higher switching losses than PWM.

Source....

http://electronicdesign.com/article...mplifiers-for-portable-applications18382.aspx

 

[mfong]

wow

I never expected what I thought was a simple question to get such complex answers. One of these times where I have to confess I barely know anything about this stuff.

 

[sendler]

TK2050 THD/power measurement shows little change

Interesting that the THD/power measurements for the Tripath TC2000/TK2050 don't show any significant increase at lower powers. Maybe the less detailed sound I am hearing at low levels is just ambient noise/ psychoacoustic related and is more noticeable now due to the incredible sonics of the Tripath chips in the Sure 2X100 amps when listening at reference levels.
http://www.sure-electronics.net/download/down.php?name=TK2050.pdf

 

[kristleifur]

Interesting that the THD/power measurements for the Tripath TC2000/TK2050 don't show any significant increase at lower powers

Interesting, but I'm not following completely - Do you mean that you would have expected higher distortion overall in the ~24V-powered graph on the left than at the right?

Maybe the less detailed sound I am hearing at low levels is just ambient noise/ psychoacoustic related and is more noticeable now due to the incredible sonics of the Tripath chips in the Sure 2X100 amps when listening at reference levels.
http://www.sure-electronics.net/download/down.php?name=TK2050.pdf

I'm always really curious as to how much the noise floor figures in the rise of THD+N at the left, at lower output power, in all of these graphs for the Tripath chips. E.g. is the distortion actually dropping at higher power, or is the distortion pretty much the same and the relative error is dropping at higher power because the noise floor is falling away?

 

[sendler]

Thd

Interesting, but I'm not following completely - Do you mean that you would have expected higher distortion overall in the ~24V-powered graph on the left than at the right?



I'm always really curious as to how much the noise floor figures in the rise of THD+N at the left, at lower output power, in all of these graphs for the Tripath chips. E.g. is the distortion actually dropping at higher power, or is the distortion pretty much the same and the relative error is dropping at higher power because the noise floor is falling away?

I would have expected higher distortion at the left side of either graph but the distortion level at 1 watt is still pretty low compared to high power. No different from most class AB THD/ power charts showing only a normal rise in the percentage of output signal that is noise at low power.

 

[kristleifur]

I would have expected higher distortion at the left side of either graph but the distortion level at 1 watt is still pretty low compared to high power. No different from most class AB THD/ power charts showing only a normal rise in the percentage of output signal that is noise at low power.

OK, yes, following now. Thanks.

 

[Eva]

In TC2000/TP2050 chipset, they way in which idle switching frequency is adjusted and the 40Khz recommended clearance between channels is screaming phase-shift oscillator in my opinion.

The way in which THD rises abruptly above -3dB is also characteristic from phase shift oscillators.

 

[phase_accurate]

The way in which THD rises abruptly above -3dB is also characteristic from phase shift oscillators.

Apart from that it would even be very difficult to design a clocked delta-sigma loop that is stable at all above -6dB.

Regards

Charles

 

[81bas]

Then I want to see some example patents from Tripath, where the sampled comparator is NOT used...

 

[phase_accurate]

Because they mention one in their patents doesn't mean that they absolutely HAVE to use one in practice. Maybe that was even done for leading the competition onto a false track.

The downside is that if suddenly someone else is doing the same thing one is left without legal protection.
OTOH you can leave a patent in the "pending" state almost infinitely in the U.S. - such that it is almost impossible to know all of the ideas that have been filed for patent - unless you work at the patent office.

I know a clever and nosey guy who might even have checked how this modulator works, maybe I'll ask him.

Regards

Charles

 

[Eva]

Well, in my self-oscillating modulator I use a sampled comparator too, but for noise rejection and reliability purposes

 

[81bas]

Well, in my self-oscillating modulator I use a sampled comparator too, but for noise rejection and reliability purposes

well, how big is the sampling frequency you used? It is definitely NOT 2-3 MHZ, right?

 

[81bas]

I know a clever and nosey guy who might even have checked how this modulator works, maybe I'll ask him.

yes, please do it

 

[Eva]

well, how big is the sampling frequency you used? It is definitely NOT 2-3 MHZ, right?

In my circuit there is no clock, the purpose of sampling is to force a minimum pulse width and prevent bouncing or parasitic self oscillation when the feedback loop becomes open.