First of all, hi to all of you !
After months of reading this classD forum I finally decided to take a shot at classD, and I settled on full-bridge UcD topology. I know, bridged UcD is not material for beginners in switching technology, but I'd still like to make one.
I plan to use Intersil's HIP4081 as gate driver and Texas Instruments TL3016 fast complementary output comparator as modulator.
Please look at first pdf
I drawed a schematic, but after looking at it carefully I realise it won't work because I have no reference for the output signal because my whole amplifier is single supply. I don't want to change the schematic to split supply, I like the idea of having only one supply rail for output stage.
Could I just use ac coupled BJT differential pair on input of the amplifier to reference the output signal to Vdd/2 ?
I read somewhere on this forum that bases of differential pair would self-bias at Vdd/2 when AC coupled ?!
Input to the modulator would then be taken from low value collector resistors of the differential pair so I don't exceed input voltage on TL3016 comparator which is powered from 5V.
look at the second pdf (in reply)
Also, I drawed RC snubbers in parallel with each output mosfet and put values of 10R and 100pF which I found in Philips UcD application note. Now i wonder if the values are right because they make highpass filter with -3dB at 159MHz. Their amplifier is switching at 400kHz. I thought the values are to be set to eat spikes and switching noise that is pretty lower in spectrum. I plan to switch at 250kHz for better efficiency and think that snubbers would have to be set to filter-out frequencies even as low as 1MHz. Is my thinking wrong ?
After months of reading this classD forum I finally decided to take a shot at classD, and I settled on full-bridge UcD topology. I know, bridged UcD is not material for beginners in switching technology, but I'd still like to make one.
I plan to use Intersil's HIP4081 as gate driver and Texas Instruments TL3016 fast complementary output comparator as modulator.
Please look at first pdf
I drawed a schematic, but after looking at it carefully I realise it won't work because I have no reference for the output signal because my whole amplifier is single supply. I don't want to change the schematic to split supply, I like the idea of having only one supply rail for output stage.
Could I just use ac coupled BJT differential pair on input of the amplifier to reference the output signal to Vdd/2 ?
I read somewhere on this forum that bases of differential pair would self-bias at Vdd/2 when AC coupled ?!
Input to the modulator would then be taken from low value collector resistors of the differential pair so I don't exceed input voltage on TL3016 comparator which is powered from 5V.
look at the second pdf (in reply)
Also, I drawed RC snubbers in parallel with each output mosfet and put values of 10R and 100pF which I found in Philips UcD application note. Now i wonder if the values are right because they make highpass filter with -3dB at 159MHz. Their amplifier is switching at 400kHz. I thought the values are to be set to eat spikes and switching noise that is pretty lower in spectrum. I plan to switch at 250kHz for better efficiency and think that snubbers would have to be set to filter-out frequencies even as low as 1MHz. Is my thinking wrong ?
Cro maniac said:
Completely.
These snubbers are intended to introduce a resistive impedance in parallel with the reactive components from MOSFET internal capacitance and package inductance, which tend to resonate above 50Mhz. Furthermore, they are not RC but RLC snubbers, their layout-dependent parasitic inductance counts too...
There should not be any ringing problems below 50Mhz, unless the supply layout and decouping is poor.
Eva, thanks for the reply, you opened new window for me 
.
Pafi, the datasheet of the HIP4081 says this:
ALI:
A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected
externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin
8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V
(no greater than VDD).
HIP 4081 provides the opportunity to control all four mosfets independently. By connecting AHI and BHI to 12V i just let the dead time set on the HIP take care of switching procedure.
Pafi, you mean I should put pulldown resistors directly on inputs of the comparator and AC couple the input resistors to preamp ? What will my common voltage reference be then ?
My greatest concern is that I have no half supply voltage reference for the outputs so I think I'll have very large offset on the output.
In dual supply amps one input of the comparator is grounded and that is reference voltage for the outputs to swing around. In my case the ground is the most negative voltage in the amp so outputs will try to work around that voltage (not good).
I thought I could buffer input signals with those two transistors i drawed in second schematic and provide reference for the output.
.Pafi, the datasheet of the HIP4081 says this:
ALI:
A Low-side Input. Logic level input that controls ALO driver (Pin 13). If AHI (Pin 7) is driven high or not connected
externally then ALI controls both ALO and AHO drivers, with dead time set by delay currents at HDEL and LDEL (Pin
8 and 9). DIS (Pin 3) high level input overrides ALI high level input. The pin can be driven by signal levels of 0V to 15V
(no greater than VDD).
HIP 4081 provides the opportunity to control all four mosfets independently. By connecting AHI and BHI to 12V i just let the dead time set on the HIP take care of switching procedure.
Pafi, you mean I should put pulldown resistors directly on inputs of the comparator and AC couple the input resistors to preamp ? What will my common voltage reference be then ?
My greatest concern is that I have no half supply voltage reference for the outputs so I think I'll have very large offset on the output.
In dual supply amps one input of the comparator is grounded and that is reference voltage for the outputs to swing around. In my case the ground is the most negative voltage in the amp so outputs will try to work around that voltage (not good).
I thought I could buffer input signals with those two transistors i drawed in second schematic and provide reference for the output.
Cro maniac!
Oops, you must be right, I didn't read the datasheet.
Yes, for example.
Nothing! It is not needed, since only the differential input controls the comparator. The only thing you have to take care about is that the inputs of the comparator should be in the normal working region.
In other words: the two input signals are the references for each other.
No! OutA + OutB=+B, this is assured by the gate-driver, so they will work around +B/2. With no input signal the inputs of comparator are on the same average potential, so it will generate 50 % duty cycle, and everything is fine.
It must work!
Oops, you must be right, I didn't read the datasheet.
Yes, for example.
Nothing! It is not needed, since only the differential input controls the comparator. The only thing you have to take care about is that the inputs of the comparator should be in the normal working region.
In other words: the two input signals are the references for each other.
No! OutA + OutB=+B, this is assured by the gate-driver, so they will work around +B/2. With no input signal the inputs of comparator are on the same average potential, so it will generate 50 % duty cycle, and everything is fine.
It must work!
Thanks Pafi, you're helping me very much
The pulldown resistors will then be effectively in parallel with the input resistors seen from the inputs of the comparator, right ? So I need to change the input resistor value so that the parallel combination of input resistor and and pulldown resistor gives me the value I had in the first case ?!
Can then the two resistors be replaced with only one input resistor that is placed between feedback and ground ?
Ok, so i just need balanced signal for feeding this amp that is not larger than Vin max (TL3016) - Vdd / Av
I like that
The pulldown resistors will then be effectively in parallel with the input resistors seen from the inputs of the comparator, right ? So I need to change the input resistor value so that the parallel combination of input resistor and and pulldown resistor gives me the value I had in the first case ?!
Can then the two resistors be replaced with only one input resistor that is placed between feedback and ground ?
Ok, so i just need balanced signal for feeding this amp that is not larger than Vin max (TL3016) - Vdd / Av
I like that
Cro maniac said:Thanks Pafi, you're helping me very much
You're welcome!
Not neccessarily. Depending on the original values, this maybe doesn't alter the feedback significantly. But originally I wanted to suggest that you should put the pulldown resistor to where now is the input. This way you don't have to recalculate anything, except for input impedance.
No. Then where would you connect the input signal?
No, input signal is not important in this context. Calculate simply DC idle voltages!
The version with the input differential amp will also work, if you use a better current source than the one you show in the schematic. I use one of the new matched dual PNP transistors from NXP for the diff-amp (PMP5501G, which is in a very small SM package) in my very similar design, with the current source set at 3mA. This gives me a very low output dc offset, which is critical in my design as I am driving a 100V step-up transformer with a very low primary dc resistance. (To drive ceiling PA speakers.)
I've not checked the phasing of your feedback paths. Double check this,as I got my first prototype PCBs wrong on this as I hadn't checked the design properly!
I've not checked the phasing of your feedback paths. Double check this,as I got my first prototype PCBs wrong on this as I hadn't checked the design properly!
It should work well, and you could do a 'UCD style' amp if you wanted as both the + and - inputs of the comparator are accessible.
Pity that's not also the case with the IRS2092. If this had the comparator connected differently internally, then this also could be used for a UCD amp, but as it stands it isn't a great deal of use for this, even though it's ideal for a pre-filter feedback sigma-delta self oscillating design.
Pity that's not also the case with the IRS2092. If this had the comparator connected differently internally, then this also could be used for a UCD amp, but as it stands it isn't a great deal of use for this, even though it's ideal for a pre-filter feedback sigma-delta self oscillating design.
I followed Luka's link; the guy opted for external comparator because of noise and "so it starts up silently when dis is removed"- checking the 4080a data sheet the comparator is not affected by the DIS pin so I fear other issues in the layout and decoupling were at the heart of the problems.
Still worth a quick try in UCD like mode- you never know!
Still worth a quick try in UCD like mode- you never know!
You don't need R-R input common mode. If you arrange your resistor values so that the self-biasing condition (allowing for the fact that the output of the amplifier will sit at an average voltage of Vsupply/2) will be at 2.5V (if your comparator supply voltage is 5V) then the actual signal swing at the input to the comparator will not go anywhere near the rails. The signal swing at the comparator input will be the audio output swing divided by the open-loop gain plus a small amount of the switching waveform. (Open loop gain is of course difficult to quantify in a UCD-style self-oscillating amplifier).
Isn't the open loop gain in ucd proportional to attenuation of the output filter at switching frequency ?
Can you please explain what you mean ?
I don't understand why would signal at the comparator inputs be audio output swing divided by the open-loop gain. If I power my amp from 60V and set gain of 12 on each side I'll have 2,5V on both inputs of the comparator at idle. But what when output goes near the rails ? Won't I have 5V at one input and 0 at the other ?
Yes, the open-loop gain is effectively that.
Regarding the swing at the actual input to the comparator. Here it is the O/L gain that matters. Just think of an op-amp. The actual differential swing directly at the op-amp input is the voltage at the op-amp output divided by the O/L gain of the op-amp at that particular frequency. In an op-amp inverter, normally the summing junction is considered as a 'virtual earth'. In reality, there is a signal at this point but it is tiny, and is the output divided by the O/L gain. In a bridged UCD circuit with differential input and differential feedback paths, then a similar state exists regarding the comparator inputs. If you SPICE it you'll see a fairly large component of the switching frequency (resulting from the post-filter ripple, and the NFB path attenuation) but a low component of the audio signal.
Regarding the swing at the actual input to the comparator. Here it is the O/L gain that matters. Just think of an op-amp. The actual differential swing directly at the op-amp input is the voltage at the op-amp output divided by the O/L gain of the op-amp at that particular frequency. In an op-amp inverter, normally the summing junction is considered as a 'virtual earth'. In reality, there is a signal at this point but it is tiny, and is the output divided by the O/L gain. In a bridged UCD circuit with differential input and differential feedback paths, then a similar state exists regarding the comparator inputs. If you SPICE it you'll see a fairly large component of the switching frequency (resulting from the post-filter ripple, and the NFB path attenuation) but a low component of the audio signal.
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