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|3rd January 2013, 04:17 PM||#41|
It is easy to imagine, if we just think about the "ENVELOPE" of a higher-frequency signal. If a singer modulated the loudness of their voice at a rate of 0.5 Hz, then on an oscillograph, we would see the higher pitch of their voice, but the peaks would be rising and falling at 0.5 Hz. Connect all of the peaks with a line and you see the 0.5 Hz envelope's waveform. Play it through a speaker and it looks like a 0.5 Hz motion. But we can note that the 0.5 Hz component is not passing through zero, like a "real" 0.5 Hz AC signal would. It's just a 0.5 Hz variation of the maximum cone displacement.
|3rd January 2013, 05:41 PM||#42|
Join Date: May 2002
Location: Great City of Turnhout, Belgium
Blog Entries: 7
Tom, followed your exposť on the cap charge current and voltage with interest, can't find anything to disagree with.
Mind if I offer an example?
Suppose your amp draws 1A from a 10,000 uF supply cap for 10milliseconds, how much does the cap voltage sag?
Your equation C*V=I*T (actually, it should all be delta's of course, but let's forget that for the moment).
So V (actually delta-V, the voltage sag) = (I*T)/C = (1 * 10^-2)/10^-2 comes out to 1 V sag. Painless
I won't make the tactical error to try to dislodge with rational arguments a conviction that is beyond reason - Daniel Dennett
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|3rd January 2013, 07:42 PM||#43|
Thank you. It's always an honor for me to even be addressed by you. I should have provided an example, in my post. But my eyes were starting to close.
I am happy that you find it interesting. I became somewhat obsessed with determining requirements for decoupling capacitor configurations, a little over a year ago. I have been sidetracked for much of the time, since then (for example, with this: )
Power Supply Resevoir Size
Power Supply Resevoir Size
But the decoupling configuration issue is still very much on my radar.
I assume that you looked at this link:
paralleling film caps with electrolytic caps
But the whole previous page in that thread is very interesting, too, starting at:
paralleling film caps with electrolytic caps
(And actually, the page before that is good, too; an interesting argument about the power supply being the main "signal path", with me railing at everyone for their "voltage centric" views of power supplies. <grin>
Anyway, as always, my goal is to be able to design for the most-faithful reproduction of the input "image", whether I like the sound or not.
One reason for the decoupling obsession (besides wanting to be able to design and lay out decoupling networks that will be sufficient to not needlessly harm the sound reproduction) is that I was "surprised" that the example calculations I performed (such as at the third link, above) seemed to indicate that, in audio power amps, it might TYPICALLY be "very difficult" to satisfy the requirement for the "maximum tolerable inductance" in a decoupling network (probably because of the connection lengths).
Or, equivalently, it might be likely that many or even most audio power amplifiers suffer from an avoidable degradation of their output sound quality, because of improperly implemented decoupling networks.
HOWEVER, since someone gets to choose the delta V, OR it gets chosen for them based on the effectiveness of their decoupling configurations, it is still possible that the problem is not a big one, or almost doesn't exist at all.
So now I'm wondering how delta V should be chosen.
|6th January 2013, 03:03 PM||#44|
Join Date: Dec 2012
|8th January 2013, 04:28 AM||#45|
While the equation will work that way, my original purpose for it was to be able to calculate the minimum decoupling capacitance needed in order to be able to supply a worst-case transient current.
In that case, we need to keep all of the deltas, and should also make it an inequality:
C ≥ Δi Δt / Δv
EXAMPLE: What is the minimum decoupling capacitance needed, for a chip's power pin, if the chip needs to be able to transition its output current from 0 Amps to 1 Amp in 10 ns, while allowing a rail voltage dip of no more than 1 Volt?
C ≥ Δi Δt / Δv
C ≥ (1)(10 x 10^-09)/(1)
C ≥ 10 x 10^-09 Farads
C ≥ 10 nF = 0.01 uF
EXAMPLE: How close to the chip's power pin would the 0.01 uF capacitance, calculated above, need to be?
L ≤ Δv Δt / Δi
L ≤ (1)(10 x 10^-09)/(1)
L ≤ 10 nH
A 10 nH inductance is roughly equivalent to 10 to 14 mm of wire or PCB trace, which must include both the power and ground connections (i.e. the total "round-trip" distance), the capacitor itself, and the chip's pins and lead-frame. The chip's lead-frame inductance could be 7 to 10 nH, by itself. Each capacitor's inductance will be approximately 0.7 nH to 1 nH times the total mm of lead-spacing plus lead lengths.
Obviously, if the ground connection is not a pin that is adjacent to the power pin being decoupled, we are in trouble. If not using a multilayer PCB with real power and ground planes, the solution would probably be to use quantity n capacitors in parallel, in an attempt to have the inductance of each cap and connection divide by n. Unfortunately, for this example, it looks like we would still need to connect them all very close to the point where the power pin enters the chip's body.
|8th January 2013, 04:54 AM||#46|
There might be a problem with that ideal equation. What about ESR?
Upon re-reading my post at paralleling film caps with electrolytic caps , I noticed that in LT-Spice, I had measured the Δi for a small, short-duration ΔV across different values of capacitors and had concluded that, within reason, the C value and the Δt were not involved, and the result was:
(1): Δi = Δv / ESR
So in the short term, and with enough capacitance, the amplitude of a current discharge from a capacitor does not depend omn the capacitance, but only depends on the voltage change and the capacitor's ESR and any other effective series resistance in the circuit.
which has a close resemblance to Ohm's Law.
I did some more simulations, with a larger range of Δt, and found that the following is true, in the more-general case, when a transient current that changed linearly from 0 Amps to Δi Amps in Δt seconds was drawn from a capacitor:
(2): V(Δt) = V(0) + Δi ( (Δt/(2C)) - ESR )
For large-enough values of C or small-enough values of Δt, equation (2) becomes equation (1), since V(0) - V(Δt) = Δv.
We could also express (2) in terms of Δv:
(3): Δv = Δi ( ESR - (Δt/(2C)) )
Last edited by gootee; 8th January 2013 at 05:03 AM.
|9th January 2013, 04:34 AM||#47|
There is a sign error in equations (2) and (3) in post # 46, and they should be:
(2): V(Δt) = V(0) + Δi ( (Δt/(2C)) + ESR )
(3): Δv = Δi ( (0.5∙Δt / C) + ESR )
Now, by solving equation (3) for C, we can get an equivalent to the first equation in post # 45, but with an ESR term, so we can also account for ESR when calculating a minimum required decoupling capacitance that will allow only up to some desired maximum rail-voltage dip Δv when a maximum specified current Δi is pulled out of the cap in a minimum specified time Δt:
(4): C ≥ (1/2)∙(Δi∙Δt ) / (Δv - (ESR∙Δi))
For an electrolytic decoupling capacitor, only, we can also substitute an approximate model for ESR that I saw, somewhere: ESR = 0.02 / (C ∙ Cap_Voltage_Rating), into equation (4) and then solve for C, again, to get an equation that includes the cap's voltage rating but not its ESR:
(5): C ≥ (Δi / Δv)∙( 0.5∙Δt + (0.02 / Vrating)) (approximation, for electrolytic capacitors ONLY)
Let's see how that might affect an example like the one that was calculated in post # 45 (except using values appropriate for an electrolytic decoupling cap):
EXAMPLE: What is the minimum decoupling capacitance needed, for a chip's power pin, if the chip needs to be able to transition its output current from 0 Amps to 10 Amps in 2 μs, while allowing a rail voltage dip of no more than 0.7 Volt?
Substituting into equation (5):
C ≥ (-10 / (-0.7))∙(0.5∙2μ + (0.02 / Vrating))
C ≥ (14.3)∙(0.5∙2μ + (0.02 / Vrating))
C ≥ 14.3μ + (0.286 / Vrating))
C ≥ 2874 μF, assuming a capacitor voltage rating of 100V.
Wow. The C value calculation is quite-dominated by the ESR-related term, in this case.
I simulated the example in LT-Spice, with 2874uF with an ESR of 0.0696 Ohms (which is 0.02 / (0.002874 ∙ 100), and the resulting Δv was -0.7 Volt.
NOTE that the C value from equation (5), for the example, is one-hundred times larger than the C value that would be calculated for the same example, using the first equation in post # 45, i.e. ignoring the ESR!
Last edited by wintermute; 9th January 2013 at 06:04 AM. Reason: fixed eq 4 per gootee's request.
|9th January 2013, 05:35 AM||#48|
SORRY. There is a sign error in equation (4) in post #47. It should be:
(4): C ≥ (1/2)∙(Δi∙Δt ) / (Δv - (ESR∙Δi))
Equation (5), there, is correct.
I have asked the moderators to correct the equation in post 47.
Last edited by gootee; 9th January 2013 at 05:43 AM.
|9th January 2013, 06:05 AM||#49|
Incredibly, in the example in post 47, I happened to end up with Δv and ESR values that would cause the denominator of equation (4) to "blow up": -0.7 + 0.696! That unfortunate choice caused the resulting C value to be extremely large.
So, for that example, if we used a polypropylene capacitor, with ESR 0.010 Ohm, we could use a 16.67 uF cap and get the same -0.7 Volt dip in the rail voltage, when drawing the same 10 Amps in 2 μs. (This result was also verified in LT-Spice.)
Obviously, we don't want to to have (Δv - (ESR∙Δi) close to zero, since it's the denominator of equation (4).
Looking at it a little differently, we could first divide both numerator and denominator by Δi:
(4a): C ≥ (1/2)∙Δt / ((Δv/Δi) - ESR)
But Δv/Δi is the same as the "target impedance" that we don't want to exceed, as seen by the points to be decoupled:
(6): Ztarget = Δv/Δi
So the denominator of (4) is telling us that we must have
(7): Ztarget > ESR
If we attempt to make Ztarget too close to the ESR, the required capacitance can go to infinity.
But Ztarget will be a specification and we get to choose capacitors with various ESR values, so instead of (7) we should probably say
(8): Use ESR << Ztarget or ESR << Δv/Δi
Last edited by gootee; 9th January 2013 at 06:34 AM.
|10th January 2013, 03:19 AM||#50|
Decoupling Capacitor Calculations
The audible signal in an electronic music reproduction system is electric current that comes directly from the reservoir capacitors of the power supply (and occasionally from farther upstream, if the rectifiers are conducting), or, whenever possible, from the decoupling capacitors nearer the power output transistors (which includes chipamps), as allowed by the modulated resistance of the power output devices, from which it flows to the speakers and then back to the power supply.
For accurate reproduction of the input signal that is used to modulate the resistance of the power output devices, the reservoir and decoupling capacitors, and the power and ground conductors, must be able to accurately provide the commanded current flow.
To try to ensure that the capacitors and conductors can always accurately provide the commanded current signal, an amplifier designer must ensure that it is at least theoretically possible for their chosen configuration of capacitors and conductors to satisfy the worst-case current amplitude and timing demands that might occur.
The capacitor equations in posts 45 through 49 were all in terms of linear (straight-line) Δi changes in the current needed from a capacitor, during a time interval Δt, and their relationships to capacitance, ESR, and simultaneous changes in the voltage across the capacitor.
Since music signals are not usually straight lines when plotted vs time, those earlier equations might be useful for planning the handling of worst-case fast transient current demands, such as square-wave edges, but they might not be as useful for ensuring that our capacitors can meet the demands of low-frequency (bass) music signals, for example, or other music signals.
All real-world music signals, and most other types of real-world time-varying signals, can be broken down into a sum of single-frequency sinusoidal components. So if we could calculate, for example, the characteristics of the capacitance and conductors needed to meet the electric current demands for the reproductions of a single sinusoidal signal, then the calculation method might be able to be extended, to enable dealing with more-complex signals.
The ideal capacitor's differential equation is:
i(t) = C dv/dt
dv/dt = i(t)/C
where dv/dt is the time rate of change of the voltage across the capacitor and i(t) is the current flowing into the designated-positive-voltage lead of the capacitor at any time t.
We can integrate both sides of that equation, in order to have v(t) instead of dv/dt:
(9): v(t) = (1/C) ∫ i(t) dt + v(0)
where the integral must be understood to be evaluated from 0 to t.
v(t) - v(0) = (1/C) ∫ i(t) dt
(10): Δv = (1/C) ∫ i(t) dt
Since the capacitor's ESR is a simple resistance, which adds a positive component to the capacitor's voltage for positive current i(t), we can include the ESR terms in the Δv equation and validate them "by inspection":
(11): Δv = (1/C) ∫ i(t) dt + ESR∙i(t) - ESR∙i(0)
That equation for Δv should be valid for any real-world current signal, i(t), at every time t >= 0.
Therefore, we could select i(t) = a∙sin(ωt), noting that the integral with respect to time of a∙sin(ωt) is -(a/ω)∙cos(ωt).
Substituting i(t) = a∙sin(ωt) into equation (11), we have
(12): Δv = (1/C) ∫ a∙sin(ωt) dt + ESR∙a∙sin(ωt) - ESR∙a∙sin(0)
Integrating and evaluating from 0 to t gives:
Δv = (-a/ωC) cos(ωt) - (-a/ωC) cos(0) + ESR∙a∙sin(ωt)
and we get
(13): Δv = (a/ωC)∙(1 - cos(ωt)) + ESR∙a∙sin(ωt)
For a decoupling capacitor, we might consider only the "leading edge" of the sinusoidal current wavefom, in which case we could think of the amplitude of the sine as Δi, giving
(14): Δv = (Δi/ωC)∙(1 - cos(ωt)) + ESR∙Δi∙sin(ωt)
But since for decoupling we might only worry about the leading edge, or rise time, we can consider only the part of a∙sin(wt) between t=0 and the first peak, which occurs when ωt = π/2.
But cos(π/2) = 0 and sin(π/2) = 1, which gives us
(15): Δv = (Δi/ωC) + ESR∙Δi
And ω = 2πf, giving:
(16): Δv = Δi∙(ESR + (1/(2πfC)))
Solving for C and setting the proper inequality gives
(17): C ≥ Δi / ( 2πf∙(Δv - (ESR∙Δi)))
Equation (17) gives the capacitance value, C, that would be required in order to supply the current for the first quarter-cycle of a sine signal of frequency f (in Hz), with 0-to-peak amplitude Δi Amperes, while causing the voltage across the capacitor to dip by no more than Δv Volts.
[Not bad for an old guy who had forgotten almost all of the mathematics he learned thirty-five years ago.]
Last edited by gootee; 10th January 2013 at 03:45 AM.
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