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Old 13th December 2012, 03:24 AM   #21
gootee is offline gootee  United States
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Quote:
Originally Posted by SirPlanALot View Post
Yes, the output Zobel is located under C1.
A MELF resistor connecting at the output trace and crossing the V+ trace, and a 0805 capacitor.
I have marked it (blue rectangle) in the attached picture.
Is the placement ok?


I moved down the row of SMD parts for about 1.4mm, to make room for an alternative footprint for C9 (Cf).
Stupidly, I didn't find any SMD capacitors in the 50pF range other than ceramics (C0G or NPO).
So, if I want to use a foil type for Cf, I will have to pick a THT part.

But I could move the other parts back upwards, where they were before.
Would that be better?


I initially planned to use the unregulated CarlosFM design and read the whole thread about it.
But then I came across the explanations of Rainwulf here on page 65: The (high-cap.) unregulated PSU for chipamps
This sounds very reasonable for me, so I think I will follow these guidelines.
It's really-great to hear that you have seen the light, in Rainwulf's excellent post! If I remember correctly, everything he said was exactly accurate and he is thinking about all of that in exactly the right ways. His post was very gratifying to read, because I have been trying to emphasize almost the same points, over and over, in this forum.

One thing that I can see that might make a significant improvement, if changed, is the local reservoir (decoupling) capacitors' configuration. The suggestion is to change the PCB area they occupy, slightly, to basically make two power planes on one side of the board and a single ground plane on the other side, and populate them with many smaller caps instead of just two larger caps, while keeping the total capacitance about the same.

This would provide several significant benefits, including lower PSU impedance (perhaps much lower) as seen by the chip's power pins, at every frequency, as well as a type of averaging and redundancy that would make the circuit much more robust against future variations in capacitor parameters. It would also increase the lifespan of the capacitors, since a larger number of smaller ones will have more surface area than one larger one, for the same total capacitance, so they will run a little cooler. Also, with smaller caps, you will be able to get some of them even closer to the power pins, which should be one of the highest-priority goals, since it reduces the inductance and resistance of the connections. (And even if you DON'T switch from one large cap to many smaller ones, you should STILL try very hard to get at least a few smaller electrolytics MUCH closer to the power pins.)

Just thinking out loud about paralleling caps: If you used n caps in parallel, even if they were all n times farther away than the original single larger cap, you could, roughly, still divide the total inductance and resistance each by n, and would have n times as much as each one's capacitance, while also NOT increasing the total conductor self-inductance or resistance at all! That would be wonderful but it gets even better. Since the n caps are each much smaller than a single large equivalent-value cap, it's extremely likely that the average connection length would be significantly LESS than n times as long, for n capacitors. So the total connection self-inductance would also be significantly reduced. i.e. There is no "downside", only significant benefits, piling on top of each other.

Actually, the same should be done for the power supply reservoir caps, which should basically be right next to the amp, too, if possible.

There is a guy named Terry Given, an extremely-bright electronics and electromagnetics engineering professional, whom we are very lucky to have on Diyaudio, who expounded on this, a while back, and also gave some brilliant yet very practical DIY construction methods (and numbers/measurements to back them up). I will try to post links to the most-relevant posts. Sorry there are so many but the result is a simple but brilliantly-better capacitor configuration.

Power Supply Resevoir Size

Power Supply Resevoir Size

Power Supply Resevoir Size

Power Supply Resevoir Size

Power Supply Resevoir Size

Power Supply Resevoir Size

Power Supply Resevoir Size

Power Supply Resevoir Size

Power Supply Resevoir Size
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Old 13th December 2012, 11:21 AM   #22
AndrewT is offline AndrewT  Scotland
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I do wish there were more of us ( and I include me in there) that have seen the light in local decoupling.

Unfortunately we are massively outnumbered by Members that won't think about the problem they embed into their PCB layouts. And worse, refuse to alter their layout when told of the poor practice they use. Why do they refuse to alter: "because it always works for me"

There is another just as important topic that is getting more airing. Small Loop Areas.
Design for small loop areas in the whole amplifier, be it an opamp, or discrete line driver, or a big power amp.
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Last edited by AndrewT; 13th December 2012 at 11:23 AM.
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Old 13th December 2012, 07:59 PM   #23
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Quote:
Originally Posted by SirPlanALot View Post
The two grounds are already separated by a resistor (R8) and two anti-parallel diodes (D1, D2). The connection point is located in the lower right corner, right from the output terminal, and under the input connector.
Now I see it! Fine

Quote:
Originally Posted by SirPlanALot View Post
Interesting, as I think about it, I'm more concerned about the Zobel resistor picking up noise from the V+ trace and leading it back to the feedback input.

Quote:
Originally Posted by SirPlanALot View Post
What about if I rotate the Zobel by 90, so that it would go downwards instead of left?
I think it would be better.

Quote:
Originally Posted by SirPlanALot View Post
Ok, I will cut the plane over the output trace.


Quote:
Originally Posted by SirPlanALot View Post
Sure, but I wonder why such low-value capacitors are not available as SMD.
I think, especially these are predestinated for SMD, to get rid of the influences of the terminal legs.
But for example the ECHU series is available from 100pf on.
They're available... from Mouser (MC12 1210 size SM)

Regarding LM3886 decoupling I would use LM3886 pads as vias so that you sit the decoupling caps on the groundplane.

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Last edited by ClaveFremen; 13th December 2012 at 08:07 PM.
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Old 14th December 2012, 01:44 AM   #24
gootee is offline gootee  United States
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Quote:
Originally Posted by AndrewT View Post
I do wish there were more of us ( and I include me in there) that have seen the light in local decoupling.

Unfortunately we are massively outnumbered by Members that won't think about the problem they embed into their PCB layouts. And worse, refuse to alter their layout when told of the poor practice they use. Why do they refuse to alter: "because it always works for me"

There is another just as important topic that is getting more airing. Small Loop Areas.
Design for small loop areas in the whole amplifier, be it an opamp, or discrete line driver, or a big power amp.
I have, for a very long time, counted you among those who truly do understand and appreciate the importance of those ideas, and was very glad that you did because you have been an untiring educator. Bravo, AndrewT.

As I think you know, minimizing enclosed loop area has been somthing that I, too, have tried to emphasize, here, over and over. Loops enclosing geometric area are antennas, both receiving and transmitting. The two worst places to have them are probably in the AC transformer and rectifier areas (transmitting), and in the sensitive signal input interconnct and amplifier input areas (receiving). Two-sided PCBs make it so simple to eliminate them in the pcb-mounted parts of a system but even then, a lot of people either don't know about it or just don't realize the critical importance of it.

Keep plugging away at them. I can't even count the number of posts I've written, trying to stress better layout techniques for minimal loop area, proper star grounding, and better decoupling capacitance configuration (and RF filtering; can't forget that).

Maybe someday I will make the time to try my ideas for hand-made multilayer PCB stacks. That would at least provide us with dedicated whole PCB layers for power and ground rails. The main key idea there is just that we would need to drill relatively large access holes, to be able to have solder joints on inner layers (and maybe also wherever "pass-throughs" were needed). It would require a bit different type of layout planning and PCB design than we do, now. But it would also give us much more freedom when designing the layout, and should eliminate a lot of potential worries, while giving almost the best-possible performance that a hand-made PCB could give.

Suddenly I'm envisioning two interspersed sets of many parallel electrolytics covering the "bottom" side, to implement a "Terry Given Super-Low-Impedance Decoupling Capacitor Array", which could be tapped-into directly at the power pins of every active chip or device, anywhere on the top side.

Or, we could forget the multi-layer stuff above and instead just try to figure out how to be able to get two cap-array boards mounted close-enough to the chipamp power pins, and connected in such a way that we don't ruin the low impedance.

The caps could be relatively small values, and the array could probably be fairly small, in terms of its board size. So maybe it wouldn't even be too difficult. I'm thinking of a 10 x 10 (or larger) array of something like 100 uF to 470 uF (for each cap in the array). Those caps could each be quite small. But how could we get the edge of their board to be right at a chipamp power pin? Maybe the cap-array pcbs would have to be vertically mounted near the bottom of the chipamp pcb, right under the chipamp.

Cheers,

Tom
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Old 14th December 2012, 11:52 AM   #25
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Thanks at all for the very valuable hints you gave, I really appreciate that!

That whole power supply topic with all that considerations should really be worth a "sticky"!
So everybody can think about it before actually designing a PCB (especially those which don't want to discard anything they've already painted in their layout software ).

I will do some planning to implement that the best way I can...

For local decoupling, there was planned one Elna RJH 470F per rail, with 12.5mm diameter.
For that diameter, the greatest capacitor value I could find was a Panasonic FR 820F with about three times better values in ripple current capability and impedance.
The next smaller diameters are 10mm with a maximum capacity of 270F, and 8mm with a maximum capacitance of 180F.

So to get the originally planned capacitance, I would have to use 2x270F or 3x180F.
I'll see if I can get that properly aligned next to the power pins...

For power supply decoupling, I originally planned to use 10,000F per rail, Panasonic TS-HA (35mm) and Elna LAH (30mm) looked the best, each with about 4A ripple current rating and ESR of 0.033.
To "array-ify" that, I would need 10x1,000F (16mm) or 5x2,200F (18mm).
Wow, this will get huge, compared to the originally planned size...
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Old 14th December 2012, 11:58 AM   #26
AndrewT is offline AndrewT  Scotland
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100uF is often adopted as the MF local decoupling. Do you have a special reason for wanting more uF?

Supply smoothing can be anywhere from 1500uF to 33mF.
You choose what suits you best, taking account of space and cost.
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Old 14th December 2012, 12:46 PM   #27
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Well, sometimes I read of making the local decoupling as big as possible.

My thoughts about it were to provide a relatively big local reservoir with low ESR and high ripple current rating.
So I would get better impulse stability before the big (and farther away) reservoir capacitance at the rectifier board can deliver current.
And of course, they fit physically just right onto the PCB.

So you think I can reduce the local decoupling without having a guilty conscience?
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Old 15th December 2012, 01:08 AM   #28
gootee is offline gootee  United States
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Quote:
Originally Posted by SirPlanALot View Post
Well, sometimes I read of making the local decoupling as big as possible.

My thoughts about it were to provide a relatively big local reservoir with low ESR and high ripple current rating.
So I would get better impulse stability before the big (and farther away) reservoir capacitance at the rectifier board can deliver current.
And of course, they fit physically just right onto the PCB.

So you think I can reduce the local decoupling without having a guilty conscience?
Maybe Andrew was only finding out how you selected the value. :-)

More capacitance (or maybe even as much as possible) COULD be better. But low impedance at the power pins is the actual goal. And capacitance is only one component of that, here. Connection lengths will add inductance and resistance. Using one larger capacitor usually gives more inductance and resistance than using several smaller ones in parallel.

Seems to me the best way would be to use the largest number of parallel capacitors that still give enough capacitance, and get all of them as close to the power pins as you can. (I would try to get three of them really close, and then keep adding more, even though they would have to be farther away.)

You could assume that you will have way more than enough capacitance, and that you will do the best-possible job placing and paralleling them so that the inductance and resistance are as low as they could possibly be. That way, you wouldn't need to calculate the minimum required decoupling capacitance or the maximum allowable inductance and resistance, because if you didn't already meet the requirements there wouldn't be anything you could do about it anyway!

But if you don't want to get extreme about adding lots of parallel caps, then you might want to do some at-least-just-ballpark calculations. On the other hand, you could just "wing it", with an educated guess, and see what happens. (And I'm not necessarily implying that's a terrible idea.)

If you do just guess, then I would probably suggest going with at least three smaller caps in parallel instead of one larger-valued one.

Cheers,

Tom
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Old 17th December 2012, 01:03 AM   #29
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Ok, I see the point.

My idea of getting one "the biggest value that fits onto the board"-capacitor was before your hint about parallelisation.

I just did some quick calculations with the Panasonic FR series:
without modifying my PCB, I could fit 4 pcs with each 6.3mm diameter per rail, instead of one with 12.5mm.

The biggest available capacity with 6.3mm diameter is 56F, with 0.405A ripple current rating and impedance of 0.14 Ohm (inductance values are not stated in the datasheet).
So if I would parallel 4 of them, I would get 224F with 1.62A ripple current and 0.035 Ohm impedance.

The corresponding value as a single cap is 220F, with 1.65A ripple current and 0.03 Ohm impedance.

My originally planned capacitor had 820F, with 3.27A ripple current and 0.014 Ohm impedance.

The (calculated) ESR values are: 2.368 Ohm for a single 56F cap, which results in 0.529 Ohm for 4 paralleled caps.
The 220F cap has 0.603 Ohm, and the 820F has 0.162 Ohm.

Hmm, doesn't look too good for the paralleled capacitors in matters of impedance...
ESR is slightly better for parallel compared to single cap with equal capacitance, but the biggest cap is ahead here too.
So the crucial point must be inductance, otherwise using parallel caps would be quite senseless...

Are my calculations wrong, or have I missed something important?

Regards, Stefan
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Old 17th December 2012, 04:41 AM   #30
gootee is offline gootee  United States
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Yeah, you missed two things. But they're really one thing. Inductance and the distance from the pins. If you used multiple smaller caps in parallel, it is assumed that would mean that they could be much closer to the pins than would be possible with one larger cap. And even if they were not closer, since the inductance of the connections would be much greater than that of the caps, the multiple parallel caps would be significantly better (assuming their connections are separate-enough from each other.

The inductance is what kills you, at higher frequencies (which includes fast-changing transients), where it will dominate the impedance, compared to the resistance due to ESR + connection length.

You can estimate the cap inductance pretty well by using 1 nH per mm, times the lead-spacing in mm. And you can estimate the self-inductance of a trace or wire with the same figure, for now. You could also try looking at an even larger number of even smaller caps.

But look at the links I posted, at least once. You could chop off the part of your PCB with the big caps and replace it with a separate 1mm-thick 2-sided PCB, maybe 48 x 48 mm. Keep one side solid copper, for ground. Divide the other side in two, by removing copper to from one slot along the diagonal. DON'T make any traces or remove any other copper, except as described. Lay out positions for 15 8 mm caps on each half (rows with 5, 4, 3, 2, and 1 cap). Drill one hole per cap, for the lead that goes to the bottom side. Remove a little copper from around each hole, on the top side. Bend the top-side lead flat against the copper and solder. One end of the diagonal "slot" will go near the chip. Connect the power pins' traces from there, with something thick or wide. Connect the rails from the PSU to the opposite corners, at the other end of the diagonal slot.

That's only one possible topology. Also, using a larger number of even-smaller caps should be even better.

Sorry I couldn't explain any of that in more detail. I have to get up early.
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