"All American" RIAA Preamp

[wrenchone]

I'm starting this thread to describe some of the work I've done with simple single ended open loop JFET and MOSFET circuits with an RIAA preamp in mind for MM cartridges. The original work was inspired by the simple "Pacific" RIAA preamp. Quite a few bows and ribbons have been added to that basic design over the past couple of years, resulting in the circuit shown below. Bits and pieces of the rationale (and some of the intervening work) are covered in the threads "Open Loop Follies, Pt. 1" and "JFET SRPP RIAA Preamp".

The scope of this investigation was deliberately limited to simple single ended circuits using a single positive supply and N-Channel devices. The test bed for all iterations used an external +40V unregulated supply, feeding a +30V regulator located on the preamp circuit board. About halfway through my investigatiions, I decided to narrow the scope of the investigation still further to a preamp using domestically made (US) JFETs and MOSFETs, out of a mixture of curiousity and sheer cussedness.

No doubt there are other topologies that may work better than the one presented here. However, the thrust of this thread is to see how much can be wrung from a single-ended design using N-Channel devices. If you want to sing the praises of another topology, please start another thread and do your singing there. Also, this preamp was made specifically for MM cartridges or high output MC cartridges, and may not be the best approach for low output MC cartridges.

The final circuit is shown in the attachment below. What I'll do in the next few days is to describe the circuit rationale, starting with a very simple circuit, and adding pieces on gradually. Simulation results will be shown for each step.

[wrenchone]

To start off with, the circuit is stripped down to a basic block diagram, reducing it to two gain blocks with a passive RIAA network in between. The first gain block is set at 40, the second at 30. This results in a gain of 40 dB at 1kHz, which suits the rest of my system pretty well. The next posts will talk about the approaches chosen for the first gain block, starting real simple and working up.

[scott wurcer]

Hey, I was cleaning my office and found that postcard you sent me. What ever happened to that Dumont O-scope? We really have to get together on one of my Left-coast visits.

[scott wurcer]

BTW, the pre-amp looks good.

[wrenchone]

The obvious gain block to start with for the first section of the preamp would be a simple common source amplifier. Since it's the first stage with a small input signal, it should use a low noise device.

A couple of other constraints apply as well. The quiescent drain voltage of the amplifier should be place somewhere near 1/2 the supply voltage, in order to ge the maximum symmetrical output voltage swing. This will help the amplifier to handle input overloads gracefully. Since this is the input section and the output voltage swing is still relatively small, you don't have to be a real fanatic about it. For example, 2V on the drain would be too low. Somewhere around 10-20V would be acceptable (15V or 1/2 the supply voltage would be perfect).

Next, you want to have a reasonable amount of bias current flowing in the JFET. This reduces noise somewhat, and also reduces distortion, as the signal current will be a small percentage of the bias current. In other words, the device characteristic won't vary too much as you're driving it. Again, this requirement is somewhat flexible - 50uA would be to low, while a few milliamps would be ok.

The device I'm using for starters is the Toshiba 2SK170, a low noise, high (relatively) transconductance N-Channel JFET. This is actually the device I started with when I first began this investigation. We'll keep with this device for the first three evolutionary steps, then look for ways to replace it.

The circuits shown in these steps will all be taken from Orcad simulations, and use the default device models availalable there. Actual devices generally be different from the simulator values in terms of Vgs, IDSS, and other parameters. The simulator allows one to quickly grasp the general features of a design. For those who follow such things, reltol was set to 0.0001, and step size was set to 20ns.

A simulation of a simple common source amplifier using the 2SK170 is shown below. A 1k resistor is placed in series with the input voltage source to approximate the resistance of a typical MM cartridge, and the 24k load resistor approximates the loading from a passive RIAA filter as used in my preamp at high frequency. With the component values shown, the gain is 38, pretty close to the target value of 40. Bias current in the JFET can be calculated from the voltage across the source resistor, and is 3.18 mA - not too bad. Calculated p-p current swing at 1mV drive is 0.076V/6k, or 12.6 uA p-p. The 24k load adds another 3 uA to this current, so the total current swing is about 15.6 uA, The signal current is about 0.5% of the bias current so one might reasonably expect the distortion to be pretty low. Quiescent drain voltage is 10.9V, which should allow enough voltage swing for anything short of a gross overload condition.

[wrenchone]

The attachment below shows the simulated distortion characteristics for the simple comon source amplifier just described. The results below shouldn't be taken as complete gospel, but can be used to look at the relative merit of a design. The THD shown is less than 0.01%, and consists almost entirely of second harmonic. This is typical of a single ended JFET amplifier at low drive levels. An actual device might exhibit somewhat higher THD, but the distribution of harmonics should be similar.

So far, so good. There are actual preamps out in the world that consist of two cascaded common source stages with a passive filter in between. The Pacific preamp is one example (a schematic is shown in the thread "Discrete Phono Preamp Designs?") . However there are other factors that must be considered in the gain block design for an RIAA preamp. I'll talk about those later....

[wrenchone]

Next thing to consider is the interaction of the input satge with the cartridge. Most MM cartridges have a high inductance (0.5 - 1H!), and are thus sensitive to the value of loading capacitance. This includes the connecting leads from the turntalble to the preamp, and also the effective input capacitance of the preamp itself. The 2SK170 has a Cgs of 30pF, and a Crss (reverse transfer capacitance of 6 pF. The Crss is multiplied by the stage gain of `40, so the input stage can pesent a capacitance of `270 pF to the cartridge, not even including the effect of the input cables. Thios means that one will be starting out with a loading capacitance that is probably greater than optimum, with no convenient way of trimming it down.

Adding a cascode stage to the input JFET reduces the multiplying effect of the input stage gain on the Crss by pinning the drain of the input (bottom) JFET at a constant voltage. The input device sets the drain current of the cascode stage. Cascoding can be accomplished by using a bipolar transistor, and there are some variations on the Pacifiic preamp that use this scheme. I prefer to use a simple sellf-biasing JFET cascode stage as shown in the attached schematic. The JFET placed on top of the bottom gain JFET sets the drain-to-source voltage of the bottom JFET. This voltage is set by the gate-to-source voltage (Vgs) of the top JFET at the bias current of the bottom FET. With this in mind , one chooses a cascode FET with an IDSS greater than that of the bottom FET, so it will running in the pinch-off region with a relatively high Vgs. I like to run the bottom FET of the cascode at a few volts to reduce the parasitic capacitances, yet not so high that the FET is operating in the region of exponential gate leakage current. This is important with the 2SK170, as the transition to exponential gate leakage current occurs at a relatively low voltage.

One good choice for a cascode FET is the PN4391. It has a relatively high breakdown voltage (40V), and a high value of IDSS. Used with a bottom FET drawing a few milliamps, it will bias that FET at 4-6V. The PN4391 is generally used as a switch or a chopper, but is also useful as a cascode. Its lower IDSS brother, the PN4393, has many uses as a linear amplifier. Both devices are readily available (fingers crossed).

The attached schematic shows a simulation of the cascode circuit described above. Operating voltages shown are very similar to real-life operation. A gate stopper resistor is included on the cascode FET to squelch any tendancy for spurious oscillation.

[wrenchone]

The gain of the circuit is not materially changed by addition of the cascode, and is ~38.5 (31.7 dB). Distortion is not radically changed, either, though the even order components are slighly increased in magnitude. Simulated distortion profile is shown below, and should be used for indication purposes only, though the trend shown is encouraging.

[wrenchone]

Next to consider is the loading effect of the passive RIAA. this load is variable, will the impedance falling as a function of frequency. The RIAA filter values are calculated assuming a stiff voltage source to drive the equalizatin netwoer. Driving the equalization network with a high impedance source will introduce error into the response curve. The output impedance of a common source amplifier is the parallel combination of the drain load resistor and the output impedance of the JFET at its given operating point.

One way to get around this problem is to use a buffer between the input stage and the RIAA network. This can be accomplihed in many ways - I chose to use an all-JFET source follower with current source loading. Utilizng the inexpensive and readily available PN4393. The imulation schematic and DC operating points are shown below. The buffer increases the overall gain of the circuit from 38.5 to 49, due to the elimination of the loading effect. If desire, one could compensate for this by lowering the value of the drain resistor on the input stage. This would also raise the drain voltage of this stage a bit, increasing the available output voltage swing.

[wrenchone]

Atached is the simulated harmonic distortion of the comon source stage with cascode and buffer. The buffer does not contribute significantly to distortion, according to the simulation.