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Old 8th April 2013, 05:43 AM   #2881
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Quote:
Originally Posted by S.A.G. View Post
This is my own interpretation of Scott's masterpiece.
Thanks for this Georgio.

Can you post a pic with what the pins of J1 & J2 do?

Also the EXACT circuit of what is on the PCB.
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Old 8th April 2013, 06:39 AM   #2882
S.A.G. is offline S.A.G.  Italy
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Hi,

I'm leaving on a business trip so it will take a couple of days before I can post the schematics. In any case, the connector pinout is:

J1-1 +VCC
J1-2 NULL/COMP
J1-3 NULL
J1-4 -IN
J1-5 +IN
J1-6 COMP

J2-1 GND
j2-2 GMC
j2-3 OUT
j2-4-VCC

The NULL pins are for easy access to offset nulling on the +VCC side. The NULL/COMP pin has double duty as it also provide access to compensation for unity gain configurations. The GMC pin is the output of the gain stage / input of diamond buffer. GND is the ground plane.

Regards

Giorgio
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Old 8th April 2013, 06:42 AM   #2883
S.A.G. is offline S.A.G.  Italy
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forgot to mention:

The NULL/COMP pin and the COMP pin are to be used together as COMP pins in unity gain configurations. A series RC network may be needed at <5x gains (according to Scott in a post lost in the thread).

Regards

Giorgio
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Old 10th April 2013, 05:28 PM   #2884
S.A.G. is offline S.A.G.  Italy
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Schematics...
Attached Images
File Type: jpg Swopa gmC.jpg (170.7 KB, 586 views)
File Type: jpg Swopa Diamond.jpg (222.4 KB, 581 views)
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Old 28th April 2013, 07:28 AM   #2885
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Default THD Construction Documentation

The attached files describe one possible implementation of the SW-OPA topology using primarily through-hole (THD) devices. They include a "clean" schematic, printed wiring board (PWB) layout, parts list with suggested sources and current (Apr 2013) cost data, and an LTSpice circuit file for simulation. I would appreciate helpful comments on the design, PWB layout, and documentation. This is a THD version of the package I submitted in Post #2656. Many of my comments in Post #2656 apply to this design and documentation; I won't repeat them here but I encourage you to review that previous post.

Changes, refinements, and departures from that previous effort include:

2. Circuit Design.
- The circuit includes both the input-stage anti-latchup diode, D1 and output-stage anti-latchup diodes D2 and D3.
- The external electrical interface consists of TEN connections: inverting and non-inverting inputs; signal output; the compensation node; signal ground; positive and negative supplies; returns for positive and negative supply decoupling; and the backside ground plane.
- Jumpers permit the signal ground, supply decoupling returns, and ground plane nodes to be connected or isolated.
- There is a jumper between the input and output sections of the circuit.

3. Component Selection.
- The input stage uses four BF862 JFET's in SOT-23 packages. The remaining transistors are primarily TO-92 packaged parts.
- The specified resistors are 1% thick film parts of RN60 type. These are rated for 1/2 watt power dissipation in commercial applications, and are physically larger than 1/4 watt resistors so there is plenty of space for substitute components.
- The specified bipolar transistors in the input stages are BC550 and BC560. These are long-established "workhorse" devices, readily available from several manufacturers at low cost.
- The KSA916/KSC2316 pair are used as the output drivers. The long-term availability of these devices is uncertain. I hope that alternatives can be identified.
- The actual output devices are either KSA916/KSC2316, or KSA1220A/KSC2690A (in TO-126 packages).

4. Printed Wiring Board (PWB).
- The PWB size is 3.937" X 2.444" (100 mm X 62 mm). It conforms to the "Sick of Beige" guidelines. (See "Sick of Beige Standard PCB sizes" at < http://dangerousprototypes.com/docs/...PCB_sizes_v1.0 > .)
- The PWB is a two-sided design.
- Most of the PWB bottom side is devoted to a shield plane. Jumpers can be used to connect this plane to the signal ground node, or an external node, or left floating
- The PWB's electrical interface uses ten swaged-in-place contact pins. The specified swage pins have a stand-off shoulder, preventing component leads and solder fillets from shorting to a chassis under the PCB assembly.
- All components are identified on the top-side silkscreen, although in a few cases the placement is somewhat ambiguous. Refer to the component placement diagrams in the PWB drawings for additional guidance.
- The output stage is laid out for TO-126 devices, and includes allowance for a clip-on heatsink. TO-92 devices can be used in the output stage if the leads are formed to fit the TO-126 pad spacing. This is straightforward for TO-92 devices having an ECB pinout. It will be more difficult for TO-92 devices with EBC or CBE pinouts and short insulating sleeves are suggested for the leads.
- The output devices and their drivers are physically adjacent to each other to facilitate thermal coupling.

Dale
Attached Files
File Type: pdf SWOPA_Post2885_Schem_Parts.pdf (184.2 KB, 158 views)
File Type: pdf SWOPA2885PWB_A_ALL.pdf (591.7 KB, 107 views)
File Type: zip Post2885_Docs_Edited_Part1.zip (790.1 KB, 56 views)
File Type: zip Post2885_Docs_Edited_Part2.zip (575.5 KB, 48 views)
File Type: zip Post2885_Docs_Edited_Part3.zip (913.0 KB, 49 views)
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Old 28th April 2013, 07:32 AM   #2886
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Quote:
Originally Posted by RNMarsh View Post
I would be interested in a thru-hole pcb that fits inside a standard 19 inch rack chassis . . .
It's a good thing we went to different schools together. I don't know if anybody under 40 really knows what "19 inch rack chassis" means.

To help with this effort, do you have favorite TO-36 transistors to use in this design?

Dale
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Old 28th April 2013, 12:12 PM   #2887
rsavas is offline rsavas  Canada
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Hi Dale,

I see that you are at it early today. I have loaded your gerber/drill data into Gerbtool and all looks fine to me. I have not done a complete examination but considering the amount of work that you have done, I can say, very well done. I take it that you have done a few designs previously :-)
One small thing to point out, I see your smallest drill/FHS is 0.016". This is fine for probably most/all fabricators. One that it will be an issue with is "batchpcb.com", which has a 0.020" FSH as a minimum, so this is what I use, if I was to use them as a fab supplier. Note, I have not used them yet.
BTW, could you post the LTspice .asc file/libs, so that I can run a sim to do some learning.
If you or anyone else is/are going to do a group buy, I'd be interested in getting a couple of pcb's to test out.
P.S. I think that you managed to make it fit into a EIA rack, have to admit, I am over 40 however.
Cheers
Rick
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Old 28th April 2013, 03:37 PM   #2888
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Outstanding! Where can I buy four boards? We've got to get a group buy going. Ray
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Old 29th April 2013, 04:19 AM   #2889
RNMarsh is offline RNMarsh  United States
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Quote:
Originally Posted by dchisholm View Post
It's a good thing we went to different schools together. I don't know if anybody under 40 really knows what "19 inch rack chassis" means.

To help with this effort, do you have favorite TO-36 transistors to use in this design?

Dale
2N174... fond memories.... No, but I have a CK722 laying around.

-RNM

Glad to get to the thru hole pcb - sanity for me. I'm in for some PCB's with thru hole parts. I think I can handle a couple smd's, if I have to.
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Old 29th April 2013, 06:35 AM   #2890
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Quote:
Originally Posted by rsavas View Post
I see that you are at it early today.
Yeah, I wanted to stick with it until the job was done - but I still forgot to attach the sim files.

Quote:
I have loaded your gerber/drill data into Gerbtool and all looks fine to me.
Thanks for running that check. I always use the built-in DRC and think REAL HARD before I override any squawks. I don't think any third-party tool has ever found a problem if I'm clean on the internal DRC but it never hurts to have a different set of "eyes" (human or electronic) look at a design before building it.

Quote:
. . . considering the amount of work that you have done, I can say, very well done.
I absolutely HATE going back to something after I have decided it's finished.

Quote:
. . . I take it that you have done a few designs previously
PWB layout was never my main job but in previous incarnations (when I had a job) I have done about a dozen PWB's from scratch, and major revisions to 4 or 5 others. The only projects I've done in this or any other hobby community are here in this thread. I had one comment that my documentation packages are far too intimidating for hobbyists.

Quote:
. . . your smallest drill/FHS is 0.016" . . . "batchpcb.com", which has a 0.020" FSH as a minimum . . .
Edit the NC Drill file to call out a 20 mil hole sted 16 mil. There's only one of the things - a via that simply refused to go away no matter which way I looked at the board or how much I cussed at it. The surrounding pad is 45 mils so there is plenty of annular ring even for a hole as large as 25 mils. I'm surprised that 16 mils is outside their process spec - even the folks at ITEAD/Seeed Studio say they can do 12 mils. I'll enlarge that via on the next pass.

(That via was in my program library from some project I did several years ago so I don't even know which vendor's requirements it was tailored for.)

You can't please everybody all the time, and PWB hole sizes is an area where you are lucky to please more than one at a time. Of course if you order 1000's of boards at a time you can get pretty much any hole size within reason, subject to the fabricator's tolerances. When you buy prototype or short-run quantities - 100 or less - you are usually restricted to the 10 or 12 hole sizes the vendor considers "standard". But no two vendors can agree on what the "standard sizes" are. Some of them will give you the closest standard hole size and others will round up to the next largest size - usually without telling you. (OK, it's somewhere in the fine print on their web page, or the work order.) In the majority of cases, especially for prototypes or manual assembly, this is quite acceptable. If not, or if the vendor insists that your documentation must match his offering, you must select the vendor before you lay out the PWB and tailor your library, and design rules, to what he provides.

Quote:
. . . could you post the LTspice .asc file/libs, so that I can run a sim to do some learning.
The LTSpice files I intended to include in the original package are attached. Note that I included a plot definitions file for the open-loop gain/phase probe. The circuit file is terribly cluttered with models for all the devices I experimented with. The Yahoo LTSpice User's Group strongly encourages placing device models on the schematic, to make the circuit file as portable as possible and avoid problems with directory structures, search path hierarchies, etc. I suggest that you copy these off into a separate file, park it in the same directory where the circuit file lives, and add an " .include " or " .lib " statement to the circuit file..

Quote:
. . . going to do a group buy, I'd be interested in getting a couple of pcb's to test out.
Is there anything like a tutorial on how to administer a group buy? I haven't seen a real paycheck in 6 months so I'm not in a position to absorb the front-end costs of creating a stockpile to be sold over many months or years.

Quote:
I think that you managed to make it fit into a EIA rack . . .
I stumbled across those "Sick of Beige" project boards I mentioned in my post, and since the PWB had to have SOME dimensions it may as well conform to one of their standard dimensions. I put an 0.10" (2.5 mm) electrical and mechanical keep-out on all four edges, so the PCB assembly could be slid into board guides or slots of appropriate dimensions. I have noticed a few companies making enclosures based on aluminum extrusions with slots specifically intended to hold a circuit board. See, e.g., Hammond 1455 series at http://www.hammondmfg.com/pdf/1455L1601.pdf .

Quote:
. . . I am over 40 however.
Old age and treachery trump youth and enthusiasm. And don't trust anyone under 30.

Dale
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