I checked it out, and was rather disappointed when I read that:
"
The greatest benefit from multiple cores is achieved when running Monte Carlo analyses and other multiple analysis modes. This applies to both SIMetrix and SIMPLIS simulators. For this application, typical performance benefit of about 75% of the core count can be achieved. So for 4 cores a Monte Carlo run may execute about 3 times faster. The SIMetrix simulator can also exploit multiple cores to gain a speedup for single runs, but the performance benefit achieved is much more modest and typically there is little benefit in having more than about 4 cores
"
More than 4 cores are thus not needed for single runs in TRAN :-(
I stay with MicroCap10.
"
The greatest benefit from multiple cores is achieved when running Monte Carlo analyses and other multiple analysis modes. This applies to both SIMetrix and SIMPLIS simulators. For this application, typical performance benefit of about 75% of the core count can be achieved. So for 4 cores a Monte Carlo run may execute about 3 times faster. The SIMetrix simulator can also exploit multiple cores to gain a speedup for single runs, but the performance benefit achieved is much more modest and typically there is little benefit in having more than about 4 cores
"
More than 4 cores are thus not needed for single runs in TRAN :-(
I stay with MicroCap10.
4 cores and 3X faster.... but also with fewer hangups. So 8 cores sounds about right for me. As cost of cores comes down and/or becomes more popular, the software developers make further improvements. So a few more cores is a good thing. Guess I'm looking for an 8 core for now and for its future advantage. Thx-RNMarsh
I presume you are referring to J17 and J18 (the input JFET's) in the diagram attached to Post 2409.
The MPF3821's specified Idss is too low (0.5 mA guaranteed minimum) to use in this circuit without extensive redesign of the entire biasing scheme. Those input devices require an Idss of AT LEAST 5.0 mA.
The 2N4416A satisfies the Idss requirement, but the forward transconductance is lower than the suggested BF862 by a factor of about 8:1. Without checking it out in simulation it's probably safe to say that the amplifier WILL amplify, but the overall performance will be measurably lower.
One interesting characteristic of this architecture that shows up in several posts along this thread is that the design seems to be relatively immune to variations among the active devices, so it may be interesting to try a pair of 2N4416A's just for the experience.
Dale
is it the architecture or the very high feedback that makes it insensitive to device variations? How much does each contribute to that characteristic? Thx-RNMarsh
well you could try Bode's sensitivity analysis - likely even taught in EE programs when you were in college
Cherry has a good paper on the subject that takes a step into nonlinearity contributions (article tests the developed estimation math against actual Hardware)
Cherry’s “ESTIMATES OF NONLINEAR DISTORTION IN FEEDBACK AMPLIFIERS” JAES V48#4 2000 p299-313 provides a method of calculating individual component distortion mechanisms contribution to overall distortion of a amplifier, more importantly it gives a intellectual framework for reasoning about distortion and feedback in a feedback amplifier.
Cherry has a good paper on the subject that takes a step into nonlinearity contributions (article tests the developed estimation math against actual Hardware)
Cherry’s “ESTIMATES OF NONLINEAR DISTORTION IN FEEDBACK AMPLIFIERS” JAES V48#4 2000 p299-313 provides a method of calculating individual component distortion mechanisms contribution to overall distortion of a amplifier, more importantly it gives a intellectual framework for reasoning about distortion and feedback in a feedback amplifier.
nah. I dont want to do that. i just want an answere from one who already knows the general answere for this topology. The assertion was that it was the topology, as i understood it. Did one do those calc against other topologies? For example in most any topology enough degeneration R will give similar insensitity to device parameters ... regardless of topologiy. A lot of gnfb can do the same thing as far as end results (distortion) is concerned... again, regardless of topology. I'm just messin' with ya... making a trivial point is all.
Thx-RNMarsh
Thx-RNMarsh
Last edited:
The biggest problem with the 4416 is the highish Vp so cascoding it is less simple. The pairing of a low Vp input device and a high Vp cascode is the easiest (just tie the gate back to the source).
The gm at 5mA of the 4416 is also lower, but the intent of this design was to get the most out of a single gm-C gain stage so there is latitude to just adjust C and see what you get. To repeat one of the points of a discrete circuit is the ability to custom compensate for each location.
I tried in the simplest way to compensate for base current errors and dynamic Ccb errors in the bipolars that's why I think there is some desensitivity to device selection (within limits of course).
Little slow right now since I seem to have a touch of the flu but I got the output board through the reflow and all seems well, bias trimmed right up and hope to repeat the open-loop performance verification.
Here’s my final breadboard with the output on top and input on the bottom, ground planes facing each other. I used standard square Vector header pins to both connect the appropriate circuit points and feed the output pins out the bottom. I fired up the output, this time I used 2N4401/4403’s only for the diamond and Panasonic DMC/DMG series pairs for the rest, essentially the same performance. At 500 Ohm load .01% thirds only open-loop. This time I tried increasing the source impedance to see how effective the cascoding is in making the loading of the output stage negligible. 200K in series with the input did nothing visible, even at 22Meg there was no visible increase in distortion. At 4KHz the magnitude of the input impedance was ~7Meg Ohms but I didn’t separate the capacitive and resistive components. The input offset current to the output stage without matching is only 227nA.
Attachments
Scott: To those of us who are not EEs, it is unclear to me which output transistors must be thermally coupled to which (bias) diamond transistor. What value should the bias pot be set before turn on ideally with the transistors that you used. What are the Panasonic DMC/DMG number of the transistors you used. Thanks for bearing with the un-initiated! Ray
OK here's the details. For the pot just trim it to 0 and power up for a minute or two and then increase pot till you add the desired current to the total supply current, no finicky probing of an internal node to adjust bias necessary. You can also play in situ and see if you can effect THD in your application. I noted the thermal tying.
The values vary slightly on the schematics simply because the exact values are not that critical (I know it drives some obsessives nuts). Like 39.2 Ohm snubbers rather than 49.9 Ohm, that trip to the bin they might have been gone. That being said I noticed the 357 Ohm resistors could be a tad larger the ratio to the position held by the 243 Ohm one should be closer to 5/3, this only adds 400uA in that branch which does not do much and comes out in the trim.
The values vary slightly on the schematics simply because the exact values are not that critical (I know it drives some obsessives nuts). Like 39.2 Ohm snubbers rather than 49.9 Ohm, that trip to the bin they might have been gone. That being said I noticed the 357 Ohm resistors could be a tad larger the ratio to the position held by the 243 Ohm one should be closer to 5/3, this only adds 400uA in that branch which does not do much and comes out in the trim.
Attachments
Last edited:
How did you determine that the ratio should be 5/3? I would have guessed that the 357 ohm resistors are almost the least-critical value in the whole design: they simply need to be small enough to ensure adequate base drive to the output devices at the full-load signal peaks (but not so small that power dissipation becomes a problem in the current source and driver devices).
What are the consequences of omitting the thermal ties (Q1 to Q4, and Q2 to Q3)? Is it primarily a bias stability problem, or are there also significant implications for signal performance? Coupling a pair of TO-92's requires a little thought when determining the layout but isn't a major problem to DIY construction. It gets more complicated to couple a TO92 driver to, say, a TO126 output device, and I think it's almost impossible to get meaningful thermal coupling between two SMT devices in this application. (To be sure, you CAN get pairs of transistors in a single SMT package but the power ratings are too low for consideration as the output devices in this circuit.)
Dale
p.s. - perhaps both these questions stem from the fact that I still don't really have a good grasp of the analytical details of the diamond buffer output stage, the advantages it provides over other output stages, etc. I'm still stuck at Fig 1 and Fig 2 of the TI (nee National Semi) App Note AN-227, where the only thing obvious is that the B-E drop of the driver stage counteracts the B-E drop of the output stage, so there is no net DC differential between the input and output terminals.
The thermal coupling does not do that much here, but if you wanted to drive 32 Ohms it shows where it might help. The bias levels are somewhat just one best guess at how to distribute a target total supply current of 25mA. Since the input runs at 5mA a side the 5/3 ratio puts 3mA in the first rank of the diamond (a little is shunted away by the bias adjust), I just thought this was a good number enough but not too much.
40dB is fine, you might want an offset adjust or servo if DC is a problem. I forgot the trim pot on these boards.
40dB is fine, you might want an offset adjust or servo if DC is a problem. I forgot the trim pot on these boards.
Last edited:
Very nice. So, a set of basic characteristics of the final SWOPA would be useful.... open loop BW/gain; thd; CMR; PSR and noise... basic all around performance numbers summary for the book. Any advice on max C load on output etc would be useful in future apps using the design. Thx-RNMarsh
Last edited:
