I don't think that counts as 'balanced' - at least not the way the author of the patent used the word.
I don't claim to fully understand the patent, but it looks like the typical 2-diode full wave rectifier as used with a center-tapped transformer is the starting point, and then the 'balanced' part is a second 2-diode rectifier of the opposite polarity. The output is taken with the center tap as the reference. I suppose it's important to note that the patented circuit is unipolar, not bipolar. Meanwhile, the redundant rectifier just feeds a resistive "dummy" load, and I kept reading the patent expecting the author to point out that the resistor should approximate the actual load fairly closely in order for the balancing effect to work properly. Quite surprised that I did not see such a comment, but I guess all's fair so long as you get your patent.
What I find slightly confusing is that the patented circuit ends up looking like the typical 4-diode full wave rectifier as used with a non-tapped transformer. There is also the claim that the leakage current through ground is minimized, but what is not fully explained is whether it matters if the output ground is ever connected to the input ground - I suppose that's what the resistor does.
The circuit that stinius provided on the left does not seem to reference the center tap except for the caps ahead of the transistors, yet the power output is taken from the (+) terminal as referenced to the (-) terminal. I don't doubt that this particular power supply is floating, but I do doubt that it has minimal leakage current across the ground, especially if the output ground has to be connected in any way to the input ground. But I admit that I'm jumping into a power supply discussion in the middle of an IV converter topic, so my apologies for the distraction.
Last edited:
Patrick
here you are http://www.diyaudio.com/forums/digi...e-nos-dac-using-tda1541a-258.html#post1750512
here you are http://www.diyaudio.com/forums/digi...e-nos-dac-using-tda1541a-258.html#post1750512
Group Buy is now open for subscription :
http://www.diyaudio.com/forums/group-buys/196585-sen-cen-all-jfet-iv-converter-evaluation-pack.html
Patrick
http://www.diyaudio.com/forums/group-buys/196585-sen-cen-all-jfet-iv-converter-evaluation-pack.html
Patrick
I believe I have to make a correction to post #119, 125 and 127.
I guess Calvin might also be caught with the same thinking error.
With a DAC that has a DC bias current, like PCM1794, 1798, or ES9018, this bias current cannot go through the current loop of the floating supply.
Rather it has to be drained from the input node and returned back to the DAC Gnd direct.
So this is best done by using a separate constant current source, and the SEN/CEN JFETs should be left as is (matched).
This constant current source can be most simply made by using a low-noise JFET (e.g. 2SK170BL) with a source resistor. I would start with a 500R trimmer, and trim it offline with an ammeter till you get the bias current you want. You may then also choose to replace the trimmer with a fixed resistor of the correct value. There are of course many constant current source around of varying complexity.
In any case, you would need to connect a separate negative power supply (simplest a 8.4V NiMH battery in parallel with an electrolytic cap)from the DAC Gnd to the JFET source resistor, in order that the JFET has sufficient Vds to function properly.
So the additional N-JFET (bias current source) has its drain connected directly to DAC i_out, its source connected to (trimming) source resistor, and its gate to the other end of the source resistor and in turn to the -ve pole of the battery.
Sounds complicated, but it is only 4 more components (JFET, trimmer, battery, cap).
No such problems with split-rail DACs like AD1865 or PCM1704 that has no DC bias current.
(I know they are not the most popular.)
Patrick
.
I guess Calvin might also be caught with the same thinking error.
With a DAC that has a DC bias current, like PCM1794, 1798, or ES9018, this bias current cannot go through the current loop of the floating supply.
Rather it has to be drained from the input node and returned back to the DAC Gnd direct.
So this is best done by using a separate constant current source, and the SEN/CEN JFETs should be left as is (matched).
This constant current source can be most simply made by using a low-noise JFET (e.g. 2SK170BL) with a source resistor. I would start with a 500R trimmer, and trim it offline with an ammeter till you get the bias current you want. You may then also choose to replace the trimmer with a fixed resistor of the correct value. There are of course many constant current source around of varying complexity.
In any case, you would need to connect a separate negative power supply (simplest a 8.4V NiMH battery in parallel with an electrolytic cap)from the DAC Gnd to the JFET source resistor, in order that the JFET has sufficient Vds to function properly.
So the additional N-JFET (bias current source) has its drain connected directly to DAC i_out, its source connected to (trimming) source resistor, and its gate to the other end of the source resistor and in turn to the -ve pole of the battery.
Sounds complicated, but it is only 4 more components (JFET, trimmer, battery, cap).
No such problems with split-rail DACs like AD1865 or PCM1704 that has no DC bias current.
(I know they are not the most popular.)
Patrick
.
Last edited:
Hi,
#125: nothing wrong with this:
Just adding, that the same applies to the SEN-circuits too. All the circuits using a floating supply need a dedicated current sink to null a DACs offset/idle/centre current. Things only change when the supplies are gnd-referenced. Then You may omit with the current sink. As example see for the SingleEnded Jocko-circuit.
jauu
Calvin
#125: nothing wrong with this:
Just adding, that the same applies to the SEN-circuits too. All the circuits using a floating supply need a dedicated current sink to null a DACs offset/idle/centre current. Things only change when the supplies are gnd-referenced. Then You may omit with the current sink. As example see for the SingleEnded Jocko-circuit.
jauu
Calvin
Last edited:
I have been asked about how to use SEN / CEN IV for balanced outputs.
Firstly, bear in mind that the SEN / CEN IV are current conveyors only, and the actual IV conversion is done passively by the Riv at the output.
In a balanced, current-out DAC there are 2 current outputs for each channel, one positive and one negative.
EACH of these outputs would need a single-ended SEN or CEN.
That means for 2 channel balanced, you need a total of 4 single-ended SEN or CEN.
There are a pair of nicely mirror-imaged SEN / CEN on each PCB, and you get 4 PCBs in total.
Therefore, you will be able to build 2 channels of balanced SEN, plus 2 channels of balanced CEN, with the evaluation pack.
Or, if you only use single ended, the evaluation pack contains sufficient PCBS to allow you to build 4 channels of single-ended SEN and 4 CEN.
The only other major cost are matched JFETs, and Riv's if you want to use fancy resistors.
But you can start off with PRP or Dale 1/4W first. And if you like the sound, you can then upgrade.
The caps costs nothing in comparison.
Unless of course you want to use unobtainium (Black Gate N or NX 47uF 16V).
Patrick
Firstly, bear in mind that the SEN / CEN IV are current conveyors only, and the actual IV conversion is done passively by the Riv at the output.
In a balanced, current-out DAC there are 2 current outputs for each channel, one positive and one negative.
EACH of these outputs would need a single-ended SEN or CEN.
That means for 2 channel balanced, you need a total of 4 single-ended SEN or CEN.
There are a pair of nicely mirror-imaged SEN / CEN on each PCB, and you get 4 PCBs in total.
Therefore, you will be able to build 2 channels of balanced SEN, plus 2 channels of balanced CEN, with the evaluation pack.
Or, if you only use single ended, the evaluation pack contains sufficient PCBS to allow you to build 4 channels of single-ended SEN and 4 CEN.
The only other major cost are matched JFETs, and Riv's if you want to use fancy resistors.
But you can start off with PRP or Dale 1/4W first. And if you like the sound, you can then upgrade.
The caps costs nothing in comparison.
Unless of course you want to use unobtainium (Black Gate N or NX 47uF 16V).
Patrick
> when use SEN / CEN with pcm63 (+-2mA) and pcm1704 what Is optimal Idss for jfets
I would recommend 8mA to 10mA in both cases.
SEN should have 4 FETs and CEN only 2, as explained in the article.
PCM63 should have 1.4k R_iv.
> also what Is schematic output DC - Is It stable over time
Output DC is zero and not subjected to JFET Idss drift, due to Kirchoff's law.
JFET drift will only after inout DC voltage.
But matching and common heatsink takes care of that.
There is nothing in the evaluation pack that has no function.
Patrick
I would recommend 8mA to 10mA in both cases.
SEN should have 4 FETs and CEN only 2, as explained in the article.
PCM63 should have 1.4k R_iv.
> also what Is schematic output DC - Is It stable over time
Output DC is zero and not subjected to JFET Idss drift, due to Kirchoff's law.
JFET drift will only after inout DC voltage.
But matching and common heatsink takes care of that.
There is nothing in the evaluation pack that has no function.
Patrick
The Pass D1 is PCM63 in balanced mode.
I am sure the schematic is either published or available if you ask Nelson nicely.
http://www.passlabs.com/pdfs/old product manuals/d1_om.pdf
Patrick
I am sure the schematic is either published or available if you ask Nelson nicely.
http://www.passlabs.com/pdfs/old product manuals/d1_om.pdf
Patrick