I was thinking two 5V power supplies, NVE and TX would be combined on one board and would be supplied by their own LDO.
I don't entirely understand the LVDS solution here but I was wondering if there was the possibility that the output of this daughter board would still provide u.fl connectors?
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Hi Rod, your card have DFU implemented, no problem! It would also had the new daughter board if it would made in time.
@ Corpius and juanitox: thank you for confirming the delivery of your cards. It will make my life easier as tracking registered parcels often it proves quite difficult from my side.
Yes, for non-isolated I2S outputs. I see you've done that later
Now, regarding the updates: besides DFU (for which I have to upload some files in the driver's package and is done) I want to build a daughter card to improve the SQ by retiming the I2S signals while adding isolation between the outputs and WaveIO board itself. This new card is designed explicitly for actual WaveIOs as the revision will not need it. I'm now in schematic stage, searching for parts that offers a fair balance between quality and performance. Moreover, to keep costs down this board will be build in Q's over 50 pcs. or more. If there's any interest in it among actual WaveIO owners please contact me through PMs.
Kind regards,
L
What is DFU
?
@Lucian:
I would like to sign up for the daughter board as well ... but it would be great to know fist your thoughts on the following possibility: synchronous/asynchronous connection to a Buffalo II/III DAC
As you well know, Ian´s re-clocking FIFO board can be connected in both modes to a Buffalo DAC. I´d love to see something similar in your daughter board
Cheers
Pepe
I would like to sign up for the daughter board as well ... but it would be great to know fist your thoughts on the following possibility: synchronous/asynchronous connection to a Buffalo II/III DAC
As you well know, Ian´s re-clocking FIFO board can be connected in both modes to a Buffalo DAC. I´d love to see something similar in your daughter board
Cheers
Pepe
I do not know how famous it is but thank you for your kind words
1. The simple answer is: no
... and that's because WaveIO needs two type of Master Clock signals for I2S output ports: 44.1 Khz and 48 Khz families clock sources. I only got 48 khz from your generator (by dividing with 768) but what happens if you play 44.1 file or from the same family? 2. Yes, it does! Looking at the pictures on the the first post of this thread you'll see J9 pin-header (on the bottom-left corner of the card). There are signals for 44.1, 48, 88.2, 96, 176.4 and 192 sample rates. In addition you'll have "Host Active" (when plugged into USB port and detected by host) and "Audio Stream" (when play something).
Noted, thank you!Hi Lorien
count me in for 1 x daughter board.
sounds interesting
No
There will be separate PSUs for each section. The goal is to provide double isolation to the I2S signal. I would say more but I'm afraid of saying stupid things in case that this new board will no work as expected .Yes, there will be U.FLs as they are now in WaveIO. I'm thinking to add W.FL as well (in the same Footprint - hoping that it will work!). We will see.
Yes.
Got it. I cannot use that binary code as it's designed for stock XMOS board and WaveIO is 0.1% different (other pin assignments and so on) thus it will definitelly Not work. I have to make it my own. One at a time...
Noted, multumescHi Lorien
count me in for 1 daughter board.
Thanks.
!Kind regards,
Lucian
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I think the only change you need to use the WaveIO with BII/BIII in sync mode is a modification the DAC board.
Even if I do love both designs: BIII + Ian's FIFO and have great respect for the designers, my daily job didn't allowed me more free time to look over these designs in searching for this synchronous approach thus it's a little over my head. I saw something here:
Update on Oversampling Bypass H i F i D U I N O
(I hope I'll not break any DIYaudio forum rules)
.. and under "Synchronous Clock" I read some details quoted below:
Okay, if there's need for a master clock signal, synchronous to incoming BCLK then it can be provided but @ what freqs?: I could source (22.5792 and 24.576 MHz) or (45.1584 and 49.152 MHz). Unfortunately 90.3168 or 98.304 MHz are way over what I'm thinking off. I need some help here...
Thanx! L
Lucian,
take a look at the following post .... it seems Ian have already figured it out and has a working solution :
Post #542 of http://www.diyaudio.com/forums/digital-line-level/192465-asynchronous-i2s-fifo-project-ultimate-weapon-fight-jitter-55.html#post3027495
It seems that his board can work in double speed mode which could allow XO frequency go up to 45.1584 MHz and 49.1520.
If you have a chance, take a look to post #542 and tell what you get from there.
Cheers,
Pepe
take a look at the following post .... it seems Ian have already figured it out and has a working solution :
Post #542 of http://www.diyaudio.com/forums/digital-line-level/192465-asynchronous-i2s-fifo-project-ultimate-weapon-fight-jitter-55.html#post3027495
It seems that his board can work in double speed mode which could allow XO frequency go up to 45.1584 MHz and 49.1520.
If you have a chance, take a look to post #542 and tell what you get from there.
Cheers,
Pepe
Double speed mode is not crucial for synch mode, just that anecdotal evidence for the es901x ESS dacs has been that sound quality improves with higher clock frequencies.
You can apply the modification to the BII/BIII and connect the WaveIO and you will only miss 384kHz and 352.8kHz sample frequencies.
Lucian has said it may be possible to modify waveio to have faster 45.1584 and 49.152MHz clocks which would give you the equivalent of Ian's 'double speed mode'. Is that what you're asking about? These faster clocks might be a default option on the daughter board for the waveio but still are not mandatory for 'synch mode'.
There isn't much magic to synch mode from what I know, other than that the off the shelf oscillators are not in convenient frequencies above 50MHz. It is a matter of preference and how much you trust the ESS internal oversampling and re-clocking or a compromise on a lower MCLK.
You can apply the modification to the BII/BIII and connect the WaveIO and you will only miss 384kHz and 352.8kHz sample frequencies.
Lucian has said it may be possible to modify waveio to have faster 45.1584 and 49.152MHz clocks which would give you the equivalent of Ian's 'double speed mode'. Is that what you're asking about? These faster clocks might be a default option on the daughter board for the waveio but still are not mandatory for 'synch mode'.
There isn't much magic to synch mode from what I know, other than that the off the shelf oscillators are not in convenient frequencies above 50MHz. It is a matter of preference and how much you trust the ESS internal oversampling and re-clocking or a compromise on a lower MCLK.
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Thank you for the explanation @hochopeper, it is really appreciated. That is exactly what I am looking for, 45.1584 and 49.152MHz clocking (maybe doubling the frequency at the daughter board).
To me the final judge is my ear and so because I tested syn versus async with the Buffalo ... I prefer sync at 50Mhz than async at 100 Mhz, it simply sounds nicer to me.
cheers and thank you again
Pepe
To me the final judge is my ear and so because I tested syn versus async with the Buffalo ... I prefer sync at 50Mhz than async at 100 Mhz, it simply sounds nicer to me.
cheers and thank you again
Pepe
Not sure...
Well, ESS says that for proper operation at 192 kHz in sync mode, the masterclock should be >192fs, so that means >36.864 MHz. 45.1584 and 49.152 oscillators should work well for 176.4 and 192, and double those rates if one wants to have "proper" performance at 352.8/384. That said, I am using an XMOS based interface right now, with 22.592 and 24.576 oscillators and it does work with the Buffalo, sync mode, at 176.4 and 192 rates.
Remember also, with the ESS chip one is still "trusting" ESS' oversampling abilities, even in sync mode, as the DAC is still oversampling to much higher rates, it is just not using its async sample rate converter stage.
I am pretty sure that Russ at TPA is planning on using ~90MHz rate oscillators for his XMOS based design, in order to get the best possible performance out of the ESS 9018 all the way up to 384 sample rates.
Well, ESS says that for proper operation at 192 kHz in sync mode, the masterclock should be >192fs, so that means >36.864 MHz. 45.1584 and 49.152 oscillators should work well for 176.4 and 192, and double those rates if one wants to have "proper" performance at 352.8/384. That said, I am using an XMOS based interface right now, with 22.592 and 24.576 oscillators and it does work with the Buffalo, sync mode, at 176.4 and 192 rates.
Remember also, with the ESS chip one is still "trusting" ESS' oversampling abilities, even in sync mode, as the DAC is still oversampling to much higher rates, it is just not using its async sample rate converter stage.
I am pretty sure that Russ at TPA is planning on using ~90MHz rate oscillators for his XMOS based design, in order to get the best possible performance out of the ESS 9018 all the way up to 384 sample rates.
