On a clc do you get the higher peak voltage of a capacitor input filter.E DC =1.4 x peak rms. But average voltage is lower. E DC =.9 x E AC. And lDC its .64 x I AC.
Choke input, everything is more alike. Peak and average E DC is .9 x E AC
But with a clc do you get the higher current benfits and a choke input filter? For a choke input filter its I Dc = .94 x I AC?
I think I got that right, LOL.
Nick
Choke input, everything is more alike. Peak and average E DC is .9 x E AC
But with a clc do you get the higher current benfits and a choke input filter? For a choke input filter its I Dc = .94 x I AC?
I think I got that right, LOL.
Nick
Power is measured in watts and you compute it by multiplying volts time amps. For a given transformer power will be the same. In other words if you get more volts then you get less amps and vice versa.
If this were not the case then you'd have a source a free power, Patent it and you'll be rich.
Actually transformers are rated by "VA", slightly different from watts but "close enough".
A good picture to have is that the choke input filter allows the rectifier to draw current from the secondary winding throughout a much longer portion of each half sine cycle. If you get to see a measured current waveform for a capacitor input filter, you will notice the very brief portion of the waveform where current is being passed. In contrast, a diode-resistor load on a transformer secondary would draw current over a complete half-cycle.
This is another way of visualising power factor - a diode-resistor load draws current over a complete half-cycle, and effectively gives PF=1. But as you shorten the portion of the half-cycle where current is passed, then PF reduces. This is the 'distortion' aspect of PF - as compared with the 'phase shift' aspect which most people normally just come across.
This is another way of visualising power factor - a diode-resistor load draws current over a complete half-cycle, and effectively gives PF=1. But as you shorten the portion of the half-cycle where current is passed, then PF reduces. This is the 'distortion' aspect of PF - as compared with the 'phase shift' aspect which most people normally just come across.
So if we want to reduce the B+ in a CLC by reducing the uf of the first C to single digits or sub 1 uf, is it possible to stress a CLC rated choke more than spec? I'm assuming that as the value of the first cap heads toward zero, we are are morphing into an LC topology, which at some point would require an LC related choke.
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