I've read somewhere that the newer board does have dual clock rate, that is 45.xxx/49.xxxMHz is that right?
I think hardware is the same, a firmware upgrade will enable it, I haven't checked in a few weeks but I haven't seen the firmware to enable the 45/49MHz input via mclk-in pin.
I wonder if you'll get any improvements by doing all that.....especially with all the new wiring you'll have floating around.....you might add more noise/problems than you're trying to take away.
So true...
The only way to really improve the stuff is to use external oscillators on a well-made PCB, with attention to signal integrity stuff, with a good filtering of I2S coming out of Amanero's board, and with proper feed of the DAC with the MCLK (or whichever matters for jitter) signal.
The best place for these oscillators is a DAC board - this way you don't have too many ways to screw the things up.
FYI, I've soldered a couple of very low ESR electrolytics (3300 uF) across the two caps that filter the crystals as well as a low ESR electrolytic across the cap that filters the CPLD supply and the cap that is directly connected to the USB 5VDC supply (both 330uF).
Mounting the CPLD and USB electrolytics was slightly positively audible (slightly more calm & relaxed sound) whereas the caps across the crystals was really audible - much larger and more differentiated soundspace, more relaxed, better flow of details & nuances.
To reduce inductance etc. I've kept pin lengths of the electrolytics to an absolute minimum.
Greetings,
Jesper
22/24 oscillators on all of my boards from latest GB.
Maybe on the MCLK_IN pin... Yet i'd like to go 11/12meg as they tend to have better phase noise specs than 22/24 and are easier to design than 45/49 megs
Are you referring to the clock inputs on the cpld or are there a new hardware revision that allows for external clock injection on the pin-header?
Whats the number of vregs currently? or better to rephrase,
what voltages are in play? 3.3v must be mandatory, so are both xos and smds powered by same reg?...i dont have dmm nearby, nor the board so..it might take me a while to measure everything.
taking the regs out,or at least usb power wont be a problem...but separating power leads to everything will be unless they are already separated :/
plus replacing at least one xo with a better one will be pita i believe
yaaaay just took a look at the photo of the boards...seems like ferrite beads to each xo, that makes job easier.
Atmel can operate from 1.6V to 3.6V with 1.8V core voltage, might be an overkill to use a seperate 1.8V reg, internal one should suffice. Xilinx 1.8v to 3.3v
- all according to datasheets.
I'm not sure of smaller smds namely V1 and U3,while Y1 should be an 12mHz USB clock
what voltages are in play? 3.3v must be mandatory, so are both xos and smds powered by same reg?...i dont have dmm nearby, nor the board so..it might take me a while to measure everything.
taking the regs out,or at least usb power wont be a problem...but separating power leads to everything will be unless they are already separated :/
plus replacing at least one xo with a better one will be pita i believe
yaaaay just took a look at the photo of the boards...seems like ferrite beads to each xo, that makes job easier.
Atmel can operate from 1.6V to 3.6V with 1.8V core voltage, might be an overkill to use a seperate 1.8V reg, internal one should suffice. Xilinx 1.8v to 3.3v
- all according to datasheets.
I'm not sure of smaller smds namely V1 and U3,while Y1 should be an 12mHz USB clock
Is the groupbuy for the amanero usb to i²S still open? I want to use it with comming subbu v3 dac.
Or is there someone in GER who has one spare?
Thank you in advance.
I think GB5 is closed and you have to wait for GB6
https://docs.google.com/spreadsheet/ccc?key=0AmX4TyHWgSmNdE5laDJQNlA3UVBYaWlrczJwYS1EcXc#gid=0
Not a brand new hardware revision, but a new cpld firmware which will turn the mclk into input - the preset is already in the configurator utility, we've gotta wait for more information from Amanero.