UcD output stage current sensing

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zilog

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Joined 2005
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soongsc said:
So this means it's also going to mimize startup transient outputs?
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The amp has (on a separate breadboard) start-up delay, all protection measures also trigger restart of this delay. This is implemented with a few BJTs, logic gates and a 74HC123 which controls the differential stage current source of the UcD. No pop whatsoever is heard using this technique.
 
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