Hawksford shows another "error correction" approach:
http://www.diyaudio.com/forums/showthread.php?s=&threadid=34719
http://www.diyaudio.com/forums/showthread.php?s=&threadid=34719
Bricolo said:
You can probably gain some more dB's by tweaking the resistance and choosing a new generation "Hi-Fet". At this level, however, the simulation results will have to be taken with a pinch of salt. To confirm the results, you'll need to build a model and make real measurements.
LV
boholm said:
From what I've seen in sim results, there's an optimalpoint arount 10mA for a BJT. I don't know why the performance doesn't increase further when I increase the bias
jcx said:
Yes I know this one, but I think the compensation is for the Vbe modilation. He regulates Vbe so the input voltage is constant-> really low input impedance. I'm not sure that other non linearities are compensated
Elvee said:
I'll tru that, where can I learn more about those Hi-Fets?
Of course, -130dB isn't realistic for a real measurement. But my point is that if you can lower the distortion from -80 to -130 in simulations, you can also expect a nice real improvement
A few notes (since I already did a similar design) :
- CFPs like to oscillate. I built one with CFPs and it was a nice RF oscillator.
- If your simulator gives you -120 dB distortion, you should check that it models all the transistor defects like : parasitic capacitance variation with voltage and temperature ; signal-induced die temperature variation ; variation of hFe and Vbe with Ic, Vce and die temperature, etc.
JFETs are nice because there is no "base" current. Or is there ? Yes there is source current ; but instead of being Ic/hFe it's d(Vgd)*Cgd so check out your paratitic capacitances. You can cascode the JFET but in this case, where does the cascode base current go ? It is better to consider the base current as an "error" current and reinject it in the circuit.
- CFPs like to oscillate. I built one with CFPs and it was a nice RF oscillator.
- If your simulator gives you -120 dB distortion, you should check that it models all the transistor defects like : parasitic capacitance variation with voltage and temperature ; signal-induced die temperature variation ; variation of hFe and Vbe with Ic, Vce and die temperature, etc.
JFETs are nice because there is no "base" current. Or is there ? Yes there is source current ; but instead of being Ic/hFe it's d(Vgd)*Cgd so check out your paratitic capacitances. You can cascode the JFET but in this case, where does the cascode base current go ? It is better to consider the base current as an "error" current and reinject it in the circuit.
By the way, the problem of base current has been mentionned, as well as the too high impedance at a Jfet's source.
No one mentionned MOSFETs, what's wrong with those? Impedance at the Gate is almost infinite, and the transconductance is higher than Jfets (so the Source impedance will be lower)
Peufeu, do you have any clues about reinjecting the base error current?
No one mentionned MOSFETs, what's wrong with those? Impedance at the Gate is almost infinite, and the transconductance is higher than Jfets (so the Source impedance will be lower)
Peufeu, do you have any clues about reinjecting the base error current?
You have to look into the documentation of semiconductor manufacturers; JFets made using the normal planar process have very predictable characteristics: an average small signal model will typically have a Vp of 5V, Idss of 10mA and gfs of 5mA/V. All these parameters are interdependent and do not vary from one manufacturer to the other. I you opt for a higher gfs (good in your case), you'll also have to accept a higher Idss and Vp, and because you'll have to operate it at the lower end of its characteristic, you'll end with similar results.Bricolo said:
Some manufacturers have introduced new processes that overcome this limitation; the denomination varies from one maker to the other.
Here is an example from NXP, formerly Philips (bloody name changes!):
http://www.nxp.com/pip/BF861A_BF861B_BF861C_4.html
Note the low Vp, high gfs and moderate Idss.
A word about MOS: from my experience, when they're used in small signal conditions, they tend to show a very high noise characteristic; it may be due to their silicon grid. You might try with a conventional Al grid model, but it will be difficult to find a enhancement type. You can play with depletion-types, such as the 40673 or other VHF models, but I think the results will be undistinguishable from a Jfet.
LV
Re: Re: Re: Transistor linearization methods
Sorry Lineup, I did of course read your post and I remember it.
But my question was about the use of a MOSFET as a pass element, having a zero gate current and a low source impedance. So, not requiring linearization.
In other words: using ONE transistor, not 2 or 3
By the way, I'm still very interested in seeing schematics of what you talked about, since I'm not very sure of what you had in mind.
lineup said:
Bricolo:
No one mentionned MOSFETs, what's wrong with those?
Excuse me Bricolo, very much.
But you have not very easy to remember things, have you?
Regards and very much thank you
for remember my words
lineup
Sorry Lineup, I did of course read your post and I remember it.
But my question was about the use of a MOSFET as a pass element, having a zero gate current and a low source impedance. So, not requiring linearization.
In other words: using ONE transistor, not 2 or 3
By the way, I'm still very interested in seeing schematics of what you talked about, since I'm not very sure of what you had in mind.
boholm said:
The DAC I have in mind is the TDA1541, for optimal operation you need less than 6 Ohms.
But this should remain true for all signals, even while transient steps.
This is one of the problems I saw while simulating multi transistor configurations (from darlington to more complicated schemes): the input impedance rises a lot around a few MHz, while a single transistor has a higher input impedance but more constant, no peak.
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