We choose low Ciss device for CCS duty so to extend its PSRR in frequency. We try have heavier gfs device at the output to lower Zo. Although higher gfs leads to higher Ciss, its Crss that counts most in a follower and proper drive in keeping a good bandwidth. Substituting much wider bandwidth output components in a calculated and tested reg, can promote oscillatory behavior beyond worse Zo.
Mismatching the PSUs a little to aid small offset deviation is legitimate. That does not allow bad idss matching or heavy PSU difference to be regarded as a good practice. It would change dissipation and tracking in the pair drastically. Under 5mV offset is plenty good anyway.
The B1 Follower tolerates very much lower -ve rail voltages than what it needs to see on the +ve rail to pass symetrical high signal peaks.
You can use this feature to supply +10-5Vdc to the CCS load jFET and you will find it works.
However feeding only 5V (rather than 10Vds) to the CCS will drop the Id well below the Idss of the device. The operating current is no longer in the B1 region, it is biased at a lower current. This generates a non zero Vgs and that non zero Vgs appears as an output offset.
Feucht shows how to correct for this offset for whatever current you decide to pass through the Follower (i.e. select your own bias current). But that is not a B1. it is simply a CCS loaded jFET Follower.
The B1 uses selected pairs of Idss devices run at 100% of Idss with equal Vds so that the device temperatures remain matched at all times. This is what makes the B1 and the DCB1 unique as far as I have seen.
Trimming the regulated voltages to remove the output offset creates a Follower that is not a B1.
You can use this feature to supply +10-5Vdc to the CCS load jFET and you will find it works.
However feeding only 5V (rather than 10Vds) to the CCS will drop the Id well below the Idss of the device. The operating current is no longer in the B1 region, it is biased at a lower current. This generates a non zero Vgs and that non zero Vgs appears as an output offset.
Feucht shows how to correct for this offset for whatever current you decide to pass through the Follower (i.e. select your own bias current). But that is not a B1. it is simply a CCS loaded jFET Follower.
The B1 uses selected pairs of Idss devices run at 100% of Idss with equal Vds so that the device temperatures remain matched at all times. This is what makes the B1 and the DCB1 unique as far as I have seen.
Trimming the regulated voltages to remove the output offset creates a Follower that is not a B1.
Thank you both.
So the fets must be perfectly matched and run at Idss. If I find any differences and try to compensate using Feuch method I deviate from B1.
Also if I try to compensate by slightly adjusting PSU voltages, I get away from B1.
It is almost impossible to exactly match the fets and also the PSU differences so B1 is very difficult to set.
So the fets must be perfectly matched and run at Idss. If I find any differences and try to compensate using Feuch method I deviate from B1.
Also if I try to compensate by slightly adjusting PSU voltages, I get away from B1.
It is almost impossible to exactly match the fets and also the PSU differences so B1 is very difficult to set.
0.5mV indicates a good Idss pair of jFETs.
This also indicates that the power dissipated in each jFET is very similar which in turn tell us that the jFETs will run at very similar temperatures. Once you have that set of conditions the output offset will remain quite stable. Maybe never worse than +-0.5mV of variation from cold to hot to high Summer or whatever.
The one thing that the DCB1 will not tolerate is a draught blowing in on the jFETs unequally. That will force them to different temperatures and the output offset will wander all over the place. A near sealed box is required. Thermal coupling of the jFETs would help in a ventilated box.
And yes, I pave posted several times that the CCS loaded jFET Follower output offset is very tolerant of mismatched rail voltages. Yes it will change very slightly but it will stay very close to it's new setting. But you don't want massively different Pq across the two jFETs. That will really complicate the warming up and seasonal temperature changes.
This also indicates that the power dissipated in each jFET is very similar which in turn tell us that the jFETs will run at very similar temperatures. Once you have that set of conditions the output offset will remain quite stable. Maybe never worse than +-0.5mV of variation from cold to hot to high Summer or whatever.
The one thing that the DCB1 will not tolerate is a draught blowing in on the jFETs unequally. That will force them to different temperatures and the output offset will wander all over the place. A near sealed box is required. Thermal coupling of the jFETs would help in a ventilated box.
And yes, I pave posted several times that the CCS loaded jFET Follower output offset is very tolerant of mismatched rail voltages. Yes it will change very slightly but it will stay very close to it's new setting. But you don't want massively different Pq across the two jFETs. That will really complicate the warming up and seasonal temperature changes.
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)Prior to seeing the B1, I was keenly following the advice of other jFET users/designers and had come to the conclusion that running them high was the preferred method.
By high, I understood that to mean Id from 60% to 90% of Idss.
It was when I saw B1 that I realised that there is an advantage in some topologies to running then at 100% of Idss.
J.C. even talks about transient behaviour/performance at >100% of Idss. But, I am not in a position to comment, other than B1 uses that transient >100% region when passing signal. Maybe Pass and Curl have something in common?
By high, I understood that to mean Id from 60% to 90% of Idss.
It was when I saw B1 that I realised that there is an advantage in some topologies to running then at 100% of Idss.
J.C. even talks about transient behaviour/performance at >100% of Idss. But, I am not in a position to comment, other than B1 uses that transient >100% region when passing signal. Maybe Pass and Curl have something in common?
I chose the lower Idss fets for CCS so the upper ones are working at 99% Idss.
The differences are minimal:
Right
CCS = 10.61mA
Follower = 10.64mA
Left
CCS = 10.59mA
Follower = 10.63mA
Maybe I should have done the other way around.
Anyway I am very happy with the outcome. For a first build p2p, it is a total success.
I very much based the layout on DCB1 pcb but if I build another one, I will try to place the fets together so they are thermaly coupled.
The differences are minimal:
Right
CCS = 10.61mA
Follower = 10.64mA
Left
CCS = 10.59mA
Follower = 10.63mA
Maybe I should have done the other way around.
Anyway I am very happy with the outcome. For a first build p2p, it is a total success.
I very much based the layout on DCB1 pcb but if I build another one, I will try to place the fets together so they are thermaly coupled.
That rings a bell. Maybe you remember I was running the simplistic phono's output buffer >Idss in some builds.
I think you made the correct decision to run the upper jFET at 99.x% of Idss.
That is what I do. Does that make it correct?
swapping them puts the Id at >100% and J.C. did talk about transient current >100%, not permanent bias >100%.
There was one builder that reported back and he claimed the performance was improved by swapping over to bias >100%. I don't believe he came to the correct conclusion.
That is what I do. Does that make it correct?
swapping them puts the Id at >100% and J.C. did talk about transient current >100%, not permanent bias >100%.
There was one builder that reported back and he claimed the performance was improved by swapping over to bias >100%. I don't believe he came to the correct conclusion.
I am not sure of the technicalities, but I seem to remember that there is a gate leakage issue when some of the operating voltages around the jFET get too big. The gate leakage can get to the point of damaging the device.
Hey Salas. I'm curious about the RC Zobel used in the last posted schematics:
http://www.diyaudio.com/forums/powe...w-voltage-shunt-regulator-86.html#post2724088
Is 1uF necessary here, is will 100nF work or even 10nF? To me it seems lower capacitance is better, so the MOSFET doesn't fight with the 2.2R resistor to drive the force lines.
Andrew, I don't think there is any simple rule for shunt regulator stability. Both the CCS and the shunt have the possibility of being unstable, with one oscillating into the other or them both oscillating together. I think to be sure you want to characterize both so you know which conditions cause oscillation, and can apply the solution.
- keantoken
http://www.diyaudio.com/forums/powe...w-voltage-shunt-regulator-86.html#post2724088
Is 1uF necessary here, is will 100nF work or even 10nF? To me it seems lower capacitance is better, so the MOSFET doesn't fight with the 2.2R resistor to drive the force lines.
Andrew, I don't think there is any simple rule for shunt regulator stability. Both the CCS and the shunt have the possibility of being unstable, with one oscillating into the other or them both oscillating together. I think to be sure you want to characterize both so you know which conditions cause oscillation, and can apply the solution.
- keantoken
There is a danger that nF range there can twist the phase before zero gain beyond 90 degrees. But ideas can be tested, maybe it gives enough slack in the end, its a beta cct. Quite cheap parts-wise to test.
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