No idea.
It's a non return to zero DAC. That could cause distortion that rises with the clock frequency, but I haven't a clue why it would increase so fast, and it should depend on the flip-flop model.
If it were some internal settling issue, it should also get better with faster flip-flops.
Something on your reference, maybe?
It's a non return to zero DAC. That could cause distortion that rises with the clock frequency, but I haven't a clue why it would increase so fast, and it should depend on the flip-flop model.
If it were some internal settling issue, it should also get better with faster flip-flops.
Something on your reference, maybe?
Hi Marcel ... Appreciate your feedback, although there apparently may then not be any reason for this .. I would intuitively have expected the THD to deteriorate maybe 6 dBs per doubling of DSD rate ("any" distortion gets double representation in the time domain) but 25 dBs really is, well, a "question mark", so to speak ... Then I have been wondering if the AD7760's FFT calculations could be "fooled" by the HF noise content but normally it seems that the software's filtering works very reliably, so ... really puzzled.
I have tried the NoDACs with various PSUs (references) and it doesn't really change (only a couple of dBs). To my memory there's also plenty of setup time but I will check this out later in the day, just to be sure.
Cheers & thanks again, Jesper
I have tried the NoDACs with various PSUs (references) and it doesn't really change (only a couple of dBs). To my memory there's also plenty of setup time but I will check this out later in the day, just to be sure.
Cheers & thanks again, Jesper
It seems that noticeable degradation in performance occurs from around DSD256, possibly reaching the limits of discrete architecture. Despite various attempts, with discrete components, THD exceeding -120dB is limited to DSD128. This trend applies to both discrete and monolithic designs. As far as I know, the AK4499eq demonstrates the best characteristics. Up to DSD256, there is minimal deterioration.
In the case of discrete components, the output is an accumulation of several taps, inevitably leading to switching noise. DSD256 involves twice the switching of DSD128, making it less favorable. Noise can be eliminated by using a single tap, but since the signal level itself is small, the characteristics do not improve. With a monolithic design, switching noise should be minimal, yet degradation persists.
However, mola mola has excellent characteristics despite using clocks around 100MHz. Chord also has good characteristics relative to its tap count (though -120dB might not be attainable). Therefore, it's possible that innovative switching techniques could maintain performance up to DSD256.
In the case of discrete components, the output is an accumulation of several taps, inevitably leading to switching noise. DSD256 involves twice the switching of DSD128, making it less favorable. Noise can be eliminated by using a single tap, but since the signal level itself is small, the characteristics do not improve. With a monolithic design, switching noise should be minimal, yet degradation persists.
However, mola mola has excellent characteristics despite using clocks around 100MHz. Chord also has good characteristics relative to its tap count (though -120dB might not be attainable). Therefore, it's possible that innovative switching techniques could maintain performance up to DSD256.
@MarcelvdG : Hi Marcel,
No, as far as I know all of these FFs change data at the rising BCLK edge. Regarding setup time I have made some timing measurements on the 74AUC1G74 that is currently soldered to the board. These measurements are attached (5.6 MHz & 11.2 MHz, JLSounds board, on-board oscillators).
As far as I can see the BCLK is always right in the middle of the DATA signal so I would guess there are not any issues with this ... ? I have also tried to increase the data line series resistor (up to 1k2) to change the timing of the DATA signal arrival at the FF but no change in distortion level.
Regarding noise what I remember is that for higher DSD rates the noise floor level rises ever so slightly (just about discernible on the AD7760), yet the ultra sonic noise rise now starts at a higher frequency, similar to what Hans Polak measured in his review paper for the various DSD rates.
@xx3stksm : Thanks for chiming in
... I reckon that as DSD rates go up, the noise/distortion mechanisms responsible for the actual audio frequency distortion also goes up as a multipla of the DSD rate increase (would that be sort of right?).
However, what happens with all of the NoDAC FFs I have used is that distortion rises sharply: From ~ -105 dB THD to ~ -79 dB THD when going from DSD128 to DSD256. That is a 26 dB THD deterioration with a DSD128 to DSD256 rate change! This is what I do not understand ... ?
I've also tried changing the VDD decoupling capacitors to give maximum decoupling at the relevant frequency (11.2 MHz =>appr. 100 nF decoupling) but it doesn't really make any difference in the distortion level. And the clock distributor I use (NB3N551) is a low phase noise IC capable of 180 MHz clock frequency.
First I was thinking that maybe it was my AD7760 ADC that was for some reason confused by the high ultra sonic noise levels but I am reluctant to believe so as it normally handles noise quite well.
I know of a discrete design using a 13 GHz FF where the designer says that with this design the distortion does not go up when going up in DSD rate. And - as I understand it - the distortion level is around -100 dB. I have also been experimenting with a 2.5 GHz FF (SY55852 - current mode logic) and here the distortion level rise is slower - BUT I cannot make the basic distortion level at DSD128 go lower than ~ -85 dBs.
The 13 GHz FF has a fall/rise time (or vice versa) of 17ps/19ps ... Just thinking aloud here: Could it be that different FFs change rise/fall time distribution as a function of the clock frequency they operate at? Might this be an explanation ... ?
I admittedly am very curious as to which practical or theoretical mechanism could make this distortion rise happen? The sound, as I wrote, to my ears is extraordinary ... and, somewhat paradoxical I find the sound quality of the higher sample rates (Edit: DSD256) to be better than at DSD128. More nuances, "faster", more detail, even if the distortion level is higher (yup, puzzled myself) ...
@merlin el mago : Hi ... I have not tried out these solutions as my JLSounds board has a built-in USB isolator. Regarding higher sample rates please see my personal observations in the section just above.
Well, will end here. Puzzled I am - comments are welcome
Jesper
No, as far as I know all of these FFs change data at the rising BCLK edge. Regarding setup time I have made some timing measurements on the 74AUC1G74 that is currently soldered to the board. These measurements are attached (5.6 MHz & 11.2 MHz, JLSounds board, on-board oscillators).
As far as I can see the BCLK is always right in the middle of the DATA signal so I would guess there are not any issues with this ... ? I have also tried to increase the data line series resistor (up to 1k2) to change the timing of the DATA signal arrival at the FF but no change in distortion level.
Regarding noise what I remember is that for higher DSD rates the noise floor level rises ever so slightly (just about discernible on the AD7760), yet the ultra sonic noise rise now starts at a higher frequency, similar to what Hans Polak measured in his review paper for the various DSD rates.
@xx3stksm : Thanks for chiming in
... I reckon that as DSD rates go up, the noise/distortion mechanisms responsible for the actual audio frequency distortion also goes up as a multipla of the DSD rate increase (would that be sort of right?).However, what happens with all of the NoDAC FFs I have used is that distortion rises sharply: From ~ -105 dB THD to ~ -79 dB THD when going from DSD128 to DSD256. That is a 26 dB THD deterioration with a DSD128 to DSD256 rate change! This is what I do not understand ... ?
I've also tried changing the VDD decoupling capacitors to give maximum decoupling at the relevant frequency (11.2 MHz =>appr. 100 nF decoupling) but it doesn't really make any difference in the distortion level. And the clock distributor I use (NB3N551) is a low phase noise IC capable of 180 MHz clock frequency.
First I was thinking that maybe it was my AD7760 ADC that was for some reason confused by the high ultra sonic noise levels but I am reluctant to believe so as it normally handles noise quite well.
I know of a discrete design using a 13 GHz FF where the designer says that with this design the distortion does not go up when going up in DSD rate. And - as I understand it - the distortion level is around -100 dB. I have also been experimenting with a 2.5 GHz FF (SY55852 - current mode logic) and here the distortion level rise is slower - BUT I cannot make the basic distortion level at DSD128 go lower than ~ -85 dBs.
The 13 GHz FF has a fall/rise time (or vice versa
) of 17ps/19ps ... Just thinking aloud here: Could it be that different FFs change rise/fall time distribution as a function of the clock frequency they operate at? Might this be an explanation ... ?I admittedly am very curious as to which practical or theoretical mechanism could make this distortion rise happen? The sound, as I wrote, to my ears is extraordinary ... and, somewhat paradoxical I find the sound quality of the higher sample rates (Edit: DSD256) to be better than at DSD128. More nuances, "faster", more detail, even if the distortion level is higher (yup, puzzled myself) ...
@merlin el mago : Hi ... I have not tried out these solutions as my JLSounds board has a built-in USB isolator. Regarding higher sample rates please see my personal observations in the section just above.
Well, will end here. Puzzled I am - comments are welcome
Jesper
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I tried Amanero using free Diyinhk I2S isolator https://www.diyinhk.com/shop/outlet/19-amanero-isolator-bare-pcb.html but the SQ lowered a lot, also using FF SQ lowered a lot. At the moment I'm using a 4th order low pass filter with the same characteristic impedance of the Amanero output impedance, also FS lowered, not the típical 50kHz passing a lot of HF noise...
N. B. Amanero isn't USB powered, I use Salas BiB 3.3V with R-core power tx, Sic diodes, CMC & Mundorf M-Lytic AG
N. B. Amanero isn't USB powered, I use Salas BiB 3.3V with R-core power tx, Sic diodes, CMC & Mundorf M-Lytic AG
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@gentlevoice I meant to ask if the data going into the flip-flops change at the falling edge. Anyway, you confirmed it can't be a hold time issue.
Is there any difference between the modulators that generate the DSD? Or don't you know because you play files you bought in DSD format?
It is basically the same. I have generated 384 kHz -1 dB 1 kHz .wav files in a program called wavegene and played them back either in HQPlayer at the various DSD rates or via a software called Tascam Hi-res Editor. With HQPlayer the distortion level surprisingly varies from playback to playback whereas with the Tascam editorr the distortion level is the same from time to time - although with a couple of dB overall higher distortion than HQPlayer's (when the distortion is low).
Might that be unfeasible in this context?
Cheers, Jesper
I was just wondering whether the difference in subjective sound quality had anything to do with different modulators. Quasi-multibit modulators (at least the ones I have experience with, like this one: https://www.diyaudio.com/community/threads/return-to-zero-shift-register-firdac.379406/post-7403058 ) can solve some weird low-level artefacts, but are only usable with lots of oversampling.
Regarding your hypothesis that the ADC is aliasing: does it get better with a second order filter?
Regarding your hypothesis that the ADC is aliasing: does it get better with a second order filter?
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Good morning to both of you
@MarcelvdG :
This morning I have checked the input of the AD7760 EVB and besides the ~ 50 kHz filter I have it has a filter at 19 MHz (they call it the first aliasing point). Since I observe the biggest increase in distortion with DSD256 (11.2 MHz) wouldn't it then be lower than what (given the 19 MHz filter) the ADC may be disturbed by? And, no, I have not tried a second order filter - I likely don't have the components at hand - but an option could be to move the cut-off frequency down to e.g. 7 kHz for the RC filter. It would yield a very low frequency cut-off.
@TNT : Thank you also for your feedback. As it is I actually have tried a balanced/differential IC (CML logic), the SY55852, and although the distortion with this IC did not increase as much its basic distortion level was somewhat higher and I couldn't really improve it. Have you tried the potato semi yourself in a NoDAC configuration and found that it worked better in terms of increasing DSD rates?
Have a fine day ...
Jesper
@MarcelvdG :
This morning I have checked the input of the AD7760 EVB and besides the ~ 50 kHz filter I have it has a filter at 19 MHz (they call it the first aliasing point). Since I observe the biggest increase in distortion with DSD256 (11.2 MHz) wouldn't it then be lower than what (given the 19 MHz filter) the ADC may be disturbed by? And, no, I have not tried a second order filter - I likely don't have the components at hand - but an option could be to move the cut-off frequency down to e.g. 7 kHz for the RC filter. It would yield a very low frequency cut-off.
@TNT : Thank you also for your feedback. As it is I actually have tried a balanced/differential IC (CML logic), the SY55852, and although the distortion with this IC did not increase as much its basic distortion level was somewhat higher and I couldn't really improve it. Have you tried the potato semi yourself in a NoDAC configuration and found that it worked better in terms of increasing DSD rates?
Have a fine day ...
Jesper