Looking at post #56, I'd say you have a great result Tekko!!! Your loop 0db gain cross over is at 1MHz, which is about right for a mosfet output amp, and your loop phase margin is 60 degrees, which is ideal.
Re the switch on thump - nothing you can do about that other than fit a realy on the out put of your amp.
In any event, this looks like a great little amp now.
Re the switch on thump - nothing you can do about that other than fit a realy on the out put of your amp.
In any event, this looks like a great little amp now.
I'm moving in that direction too. There seems to be much more available in SMT now and since I make my own boards, no drilling required
half a MegaByte for one pic should be blocked/barred/banned.
The Forum needs to change it's acceptability rules.
what causes the phase "bump" between 3Hz and 500Hz? Is that audible? Does it matter?ostripper, im not sure if you saw the schematics posted last:
I have that cobbled together now on one of my boards, i did the darlington alittle ugly on top of the board with 2 transistors.
87degree phase margin, brilliant.
Does it change much when a little bit of cable capacitance is allowed for?
basic linear system theory - for "minimum phase" linear systems the phase and magnitude response are co-determinant - the fundamental principle behind Bode diagram approximations
a region of "flat" low frequency gain has 0 phase shift ultimate limit, the 1st order dominant pole region has 90 degrees phase shift - where the regions merge there is a smooth transition the phase can be calculated with Bode's Phase Integral given the magnitude plot
the amount of feedback is limited by the rate we can roll off the high audio frequency loop gain and the unity loop gain intercept that has to be below the frequencies where higher order poles cause too much phase shift
standard audio amplifier practice is to use 1st order dominant pole compensation and without extreme measures the low frequency gain becomes flat at low audio frequencies due to gain device limitations - more output stage current gain (triple follower, Mosfet), cascode VAS, reduced diff pair degeneration can all contribute to higher low frequency gain - allowing the 90 degree dominant pole slope to continue upward to the left to lower frequencies
re Picture Size:
it is considered impolite to put up oversize pictures when not everyone has high bandwidth connections or large screens - the oversize pictures can even make reading the text difficult if you have to scroll the window – portable device uses may have expensive and limited data bandwidth
so please resize/crop to <~500x500 pixels or so – or just post the link to the hi res image (not an embedded link)
It's not really a bump. The open loop gain rolls of from about 100Hz.
Then there's a low pass at around 10Hz caused by probably the feedback decoupling cap (or maybe the input coupling cap).
These are two separate things; because they are relatively close on the graph they just look like a bump.
jan didden
Well, you can't plot it, but you can "step" the frequency parameter (look in Help and at the examples). The simulation will run several times at different frequencies and the distortion will be measured each time, assuming you use a .four statement. You can then copy the results from the sim log and chart them in excel.
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