is fanout such a critical issue to jitter performance? i suppose it depends on what is driving the lines, but if we use a high enough performance buffer (e.g. the comparator in the Kwak clock) wouldn't the degradation from driving multiple lines be minimal? i think it would be good to buffer the 4th line going to the digital board, since it will be the most reactive (ribbon cable to remote board, longer traces, etc.) but shouldn't isolation resistors on the three lines be sufficient for the DACs?
dorkus said:
Hi
Mutual clock phase: I'd say both channels need same phase, but it will depend on the DAC chip, and the accepted error. BB PCM63 converts at downgoing slope at LE, so there will be small delay between both channels.
Quality of buffers, inverters: The induced jitter depends on the type of logic, and the design of the circuitry, there is no generic answer here.
Less is better, applies here as well........
enjoy
Clock
Hi Dorkus,
What's in my clock can be found here:
http://www.diyaudio.com/forums/show...e=15&highlight=marantz AND clock&pagenumber=2
From the datasheet of the AD8561:
<B>"</B>
<B>OUTPUT LOADING CONSIDERATIONS</B>
The AD8561 output can deliver up to 40 mA of outputcurrent without any significant increase in propagation delay. The output of the device should not be connected to more than twenty (20) TTL input logic gates, or drive a load resistance less than 100 Ohm.
<B>"</B>
Hope this helps.
Hi Dorkus,
What's in my clock can be found here:
http://www.diyaudio.com/forums/show...e=15&highlight=marantz AND clock&pagenumber=2
From the datasheet of the AD8561:
<B>"</B>
<B>OUTPUT LOADING CONSIDERATIONS</B>
The AD8561 output can deliver up to 40 mA of outputcurrent without any significant increase in propagation delay. The output of the device should not be connected to more than twenty (20) TTL input logic gates, or drive a load resistance less than 100 Ohm.
<B>"</B>
Hope this helps.
Re: Clock
Elso,
Nice statement from AD, but does it tell you anything on the jitter the comparator gives ?
The "static" prop delay is about 2 ns/V. Luckilly the device has a high PSRR, but that is not specified as function of frequency.
Since AD does not specify anything on induced jitter, I'd suggest to measure it.
best regards
Elso Kwak said:Hi Dorkus,
What's in my clock can be found here:
http://www.diyaudio.com/forums/show...e=15&highlight=marantz AND clock&pagenumber=2
From the datasheet of the AD8561:
<B>"</B>
<B>OUTPUT LOADING CONSIDERATIONS</B>
The AD8561 output can deliver up to 40 mA of outputcurrent without any significant increase in propagation delay. The output of the device should not be connected to more than twenty (20) TTL input logic gates, or drive a load resistance less than 100 Ohm.
<B>"</B>
Hope this helps.
Elso,
Nice statement from AD, but does it tell you anything on the jitter the comparator gives ?
The "static" prop delay is about 2 ns/V. Luckilly the device has a high PSRR, but that is not specified as function of frequency.
Since AD does not specify anything on induced jitter, I'd suggest to measure it.
best regards
dorkus said:
Dorkus,
I have heard thousands of people being enthousiastic about heavilly distorting amplifiers. At the risk of raising a different thread, the only thing that I want to make clear is that measuring at least gives more grip on the subject.
I never listened to, or measured at Elso's clock. I am sure about one thing: The lower the jitter, the better.
regards
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