Simplistic MosFET HV Shunt Regs

Q2 are cold on both boards.
But on new board I got slight dif results=

Vout = 40 V @ 88mA

Q1 Vds = 95 V
Q1 Vgs = 2,3 V

Q2 Vds = 1,7 V
Q2 Vgs = 1 V
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Felipe, going much higher at Vin only rewards by 1 or 2 mA. more.
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euro21, I understand now you duplicated the cascode, please forgive me my bad at reading in first glance.
It seems the results very close to the specification.
But is no other way than paralelling? I dislike the idea....maybe another design... one upper, I like the speed of Ixys in the upper, and two DN2540 to take the heat??
 
If you use DN2540 as "lower" FET, in the datasheet the saturation Id current at -about- 1.5V Vds, 0V Vgs is about 85mA.
That's why I suggested to use duplicated -parallel- CCS (the other reason is the Q2 limited current capacity).
I find it in the specification pdf, Is a shame that IXYS not provide also saturation Id current curves
 

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Thanks Bela, I appreciate the schems, great this one including Ixys.
I will see what can I do for an easy comparison when listening each schematic performance.. maybe a perforated board with row pins soldered and contact paste to help filling the holes.

In the meantime waiting for the parts, I succed in reply the conditions where 77V/170mA. are archieved this past days.
At the time, I have had a solder bridge Drain to Source in Q1.
So bypassing Q1, confirmed the reg is in again in working order, and good sounding without the cascode!
 
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Yes, it cancels the force wires resistance by sensing voltage for the error amp at the load's node. Sense carries no current.

Because it extends the loop area beyond the board, has to be applied with care not to become a noise antenna. So not too long & thin twisted. Or even better, coaxial sense wiring.