Return-to-zero shift register FIRDAC

Bohrok was so kind to send me a -60dB .dsf file that in his case lead to visible modulation products in his measured spectra.
Simulating this file in my LTSpice model could not show any spectral lines caused by modulation.
Like in the above posting it could be that smaller filter bins are needed to reduce the noise level, ultimately making those spectral lines visible.
But if so, is anything happening below -130dB a reason for concern ?
The other reason could be that the real analog filter isn't behaving as perfect as the LTSpice filter.
Because the AK4493 showed clean spectra with the same .dsf files, the cause is clearly the senstivity for HF noise in the filter and that's why I designed a hybrid filter that may result in a much lower sensitivity for this modulation problem.

Will show the hybrid filter tomorrow with some results from simulations.

Hans
 

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Reply to post #2700:
Well, the noise floor in the simulation is around -130 dB with respect to something and the intermodulation products bohrok2610 measured are around -130 dB DSD. However, if I understand you correctly, the FIRDAC is not included in the simulation, so neither is its suppression around odd multiples of fs/2.

That should make it a lot worse. For example, assuming 30 dB of suppression, second-order intermodulation products should get 60 dB worse, well above your simulation noise floor (*). I don't know why that doesn't happen.

By the way, it's a plain old fifth-order sigma-delta modulator without PWM.


(*): For the same reason, running the DAC at twice or some other multiple of the bit clock frequency could make the intermodulation products stronger and, hence, easier to measure. The RTZ behaviour and the spikes due to unequal propagation delay times are then retained.
 
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it’s a misunderstanding that the Firdac was not included so all suppressions as from fs/2 and upwards are there, but here I only showed the spectrum up to 30Khz.
0dB in my images is maximum output, as can also be seen in the -60dB image from the Bohrok file.
I’ll show tomorrow the whole logarithmic spectrum with all the suppressions.

So, I simulated the whole chain digital and analogue, starting by offering the split cintent of the .dsf file and the BCK to the input of the of the RTZ Firdac that includes each vital digital element, see first image in #2629.

Hans
 
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In that case, the intermodulation product will at most be around your simulation noise floor, and quite possibly below it when you have less spikes than in reality, for example due to too optimistic modelling of the shift registers.

If you want to compare different filter options to see which is best, rather than to simulate the actual distortion levels, it might be a good idea to eliminate the FIRDAC or to run it at twice the bit clock frequency.
 
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What I have is an exact copy of your shiftregister design but you are right that I have no spikes with the 0.1nsec step time in LTSpice. Is it your opininion that those spikes are causing the intermodulation products?

All flip flops now have been given the same 5nsec delay time, but I can easily change that by giving all sixteen slightly different delay times and force spikes emerging that way.
Could you give some advise what spread I should apply ?

With the Firdac in place, I already run the filters with twice the bit clock frequency, right ?
I would like to get as close as possible to reality, including those intermodulation products, only then will it be possible to see what different filters can bring.

Hans
 
With the simulated noise level at ca -130dB ref full scale, with a filter bin of 62.5Hz, the S/N calculates to -130 + 10*log(20,000/62.5) = 105.0 dB or 106.8 dBA.
This is almost within 1 dB of the value of 105.3 dB-A that I measured on the real RTZ Firdac as reported earlier.

So the model is already getting quite accurate in some ways.

Hans

P.s. I have added the logarithmic spectrum up to 16Mhz that I promised in #2703, showing odd multiples of fs/2 when processing Bohroks -60dB .dsf file.
The bit clock used had a frequency of 5.64Mhz.
 

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What I have is an exact copy of your shiftregister design but you are right that I have no spikes with the 0.1nsec step time in LTSpice. Is it your opininion that those spikes are causing the intermodulation products?

Peaks around half the sample rate and its odd multiples seem to cause the issue, even though the FIRDAC suppresses them. One reason why they leak through to some extent is the fact that they are not exactly in the notch at fs/2 but a few kilohertz higher or lower, but any FIRDAC imperfection could make it worse.

You could try giving each flip-flop 1 ns more delay from high to low than from low to high, and make the FIRDAC resistors slightly unequal.

All flip flops now have been given the same 5nsec delay time, but I can easily change that by giving all sixteen slightly different delay times and force spikes emerging that way.
Could you give some advise what spread I should apply ?

See above. It's not based on anything, the only available data are in the SN74LV574A datasheet.

With the Firdac in place, I already run the filters with twice the bit clock frequency, right ?
I would like to get as close as possible to reality, including those intermodulation products, only then will it be possible to see what different filters can bring.

Hans

I don't see why. You can still compare good and bad filters when you deliberately spoil the FIRDAC suppression by using the wrong clock frequency.
 
Thx Marcel,

I’ll first try using different delay times for up and down slopes.
Later I can eventually try a more refined individual spread in difference.

Do you mean “by using the wrong clock frequency” the bit clock ?
Doesn’t this have the sole effect of shifting everything in frequency, so with a 10% higher clock the 1Khz becomes 1.1Khz and the notches at odd multiples of fs/2 also shift by 10% ?

Hans
 
When you change the input data according to the correct bit clock frequency but run the DAC at twice the correct bit clock frequency, the data will be clocked in twice, at the normal time and half a bit clock period later. The impulse response of the FIRDAC becomes one bit clock period wide (instead of the normal two bit clock periods), but due to sampling the data twice, for each data bit, you get a staircase-shaped response of 1.5 bit clock periods wide.

I think that should eliminate the notches near half the sample rate.
 
Marcel, so I would need an extra register to take over the data with the bit clock an from thereon use twice the frequency that is used now.
The Firdac in that case should be clocked at 4 times the bitclock or still at twice the bit clock?

What benefit could be expected from eliminating notches near half the sampling rate

Hans
 
Marcel, so I would need an extra register to take over the data with the bit clock an from thereon use twice the frequency that is used now.
The Firdac in that case should be clocked at 4 times the bitclock or still at twice the bit clock?

What benefit could be expected from eliminating notches near half the sampling rate

Hans

The idea is to play each bit in the bit stream twice. I don't know whether you need an extra register for that, that depends on how you get the data into your simulation.

For example, suppose you have a 5 Mbit/s bit stream (DSD128 rounded to a round number). You would then let the DAC run at a 10 MHz bit clock, which it would double to a 20 MHz shift register clock.

The purpose is to make it easier for the simulator by much increasing the products around fs/2 that reach the analogue reconstruction filter, and thereby also increasing the intermodulation products that the filter generates, so they become visible above the simulation noise floor without needing a very small resolution bandwidth/very long simulation runs.
 
Marcel, This what I get with a delay on the downgoing slope that is 0.3nsec more than on the upgoing slope for all Firdac flip flops.
In the spectrum below, processed with the -60dB Bohrok .dsf file, you see in blue the diff output from the original Firdac filter and in red the CM signal on both 8.2nF input caps.

Next picture will be with your .dsf file with DC offset.

Hans
 

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