Hi everybody,
I’m trying to modify a Teac VRDS 25X. It uses the following chips:
CXD2545Q (CD-Decoder 16.9344MHz), AD1893 (ASRC, resamples to 48kHz with 18.432Mhz), SM5843, uPD65031 (signal conditioning for symmetrical D-A conversion, I guess), AD1862. The digital input receiver is a TDA1315H.
Beside other mods, I’d like to get rid of the AD1893. What shall I do. Replace it with AD1896 as there are replacement modules available? Or is it better to use no ASRC at all? I prefer a solution without ASRC, but this is probably more complex and I’m not sure how to do it.
Anyway, this is how the chips are connected right now:
The input format of the AD1893 (signal coming from CXD2545Q and TDA1315H is fed through some 74HC* and then goes to the ASRC) is set to serial input (16bit, I guess) / left-justified / no MSB delay / left-right clock timed. The output of the AD1893 is the same, except that word length is 24bit (16bit stuffed with zero?). This is described on page 1+18 in the datasheet.
The SM5843 is set to accept the same format (LR alternating / leading data / 20bit input) and data after LSB (bit 20) is ignored. Described on page 19 in SM5843 datasheet.
The main question is: what happens if I desolder AD1893 and directly connect BCK, LRCK and DATA (previously connected to the input of AD1893) to SM5843? The 20bit input of the SM5843 will be fed with 16bit data. Will the SM5843 fill the 4 last bits with zero? Will this work?
Of course I would also have to connect the 16.9344MHz clock to SM5843 and uPD65031. Does anybody have a datasheet of CXD2545Q or circuit diagram of Teac VRDS 25X (I’ve only got the circuit of ASRC-DF-DAC-Output-Stage)? This would be great help.
Well, that are many questions. Maybe some of you have already done something similar or have a little more experience with chip interfacing than I have, so thanks a lot for any advice,
Fabian
I’m trying to modify a Teac VRDS 25X. It uses the following chips:
CXD2545Q (CD-Decoder 16.9344MHz), AD1893 (ASRC, resamples to 48kHz with 18.432Mhz), SM5843, uPD65031 (signal conditioning for symmetrical D-A conversion, I guess), AD1862. The digital input receiver is a TDA1315H.
Beside other mods, I’d like to get rid of the AD1893. What shall I do. Replace it with AD1896 as there are replacement modules available? Or is it better to use no ASRC at all? I prefer a solution without ASRC, but this is probably more complex and I’m not sure how to do it.
Anyway, this is how the chips are connected right now:
The input format of the AD1893 (signal coming from CXD2545Q and TDA1315H is fed through some 74HC* and then goes to the ASRC) is set to serial input (16bit, I guess) / left-justified / no MSB delay / left-right clock timed. The output of the AD1893 is the same, except that word length is 24bit (16bit stuffed with zero?). This is described on page 1+18 in the datasheet.
The SM5843 is set to accept the same format (LR alternating / leading data / 20bit input) and data after LSB (bit 20) is ignored. Described on page 19 in SM5843 datasheet.
The main question is: what happens if I desolder AD1893 and directly connect BCK, LRCK and DATA (previously connected to the input of AD1893) to SM5843? The 20bit input of the SM5843 will be fed with 16bit data. Will the SM5843 fill the 4 last bits with zero? Will this work?
Of course I would also have to connect the 16.9344MHz clock to SM5843 and uPD65031. Does anybody have a datasheet of CXD2545Q or circuit diagram of Teac VRDS 25X (I’ve only got the circuit of ASRC-DF-DAC-Output-Stage)? This would be great help.
Well, that are many questions. Maybe some of you have already done something similar or have a little more experience with chip interfacing than I have, so thanks a lot for any advice,
Fabian
Thanks for your postings Ray. In the meantime I recieved the whole circuit from Alexander. Many thanks again.
Now I see that some 74HC are used to convert Philips I2S to Sony format (invert LRCK and delay DATA by 7 bitcycles) and then the three lines (BCK, DATA, LRCK) from CXD2545Q or TDA1315H are switched by a 74HC4053 as you expected. After the switch LRCK is delayed by 8 bitcycles to make the format fit the input of AD1893 (convert from right justified to left justified).
If I remove the AD1893 I just have to remove the 74HC164 that delays LRCK after the switch and set the SM5843 to "LR alternating, trailing data, 16bit input." I guess this should work.
Now I have to think about the path of the 16.344Mhz clocks. Anyway, I'll keep you updated and it's very likely that I'll have some more questions
Fabian
Now I see that some 74HC are used to convert Philips I2S to Sony format (invert LRCK and delay DATA by 7 bitcycles) and then the three lines (BCK, DATA, LRCK) from CXD2545Q or TDA1315H are switched by a 74HC4053 as you expected. After the switch LRCK is delayed by 8 bitcycles to make the format fit the input of AD1893 (convert from right justified to left justified).
If I remove the AD1893 I just have to remove the 74HC164 that delays LRCK after the switch and set the SM5843 to "LR alternating, trailing data, 16bit input." I guess this should work.
Now I have to think about the path of the 16.344Mhz clocks. Anyway, I'll keep you updated and it's very likely that I'll have some more questions
Fabian
Pin description for CXD2545Q:
LRCK = Pin45
DATA = Pin46
BCK = Pin47
In the original Teac VRDS 25X circuit the connections between SM5843 and uPD65031 consist of WCKO, BCKO, DOL, DOR and 18.432MHz clock from SM5843 Pin9 to uPD65031 Pin41.
Now that I want to remove the AD1893, I don't need the 18.432MHz clock anymore. The SM5843 and the uDP65031 need to be fed by the 16.9MHz of CXD2545Q or TDA1315H.
Fabian
LRCK = Pin45
DATA = Pin46
BCK = Pin47
In the original Teac VRDS 25X circuit the connections between SM5843 and uPD65031 consist of WCKO, BCKO, DOL, DOR and 18.432MHz clock from SM5843 Pin9 to uPD65031 Pin41.
Now that I want to remove the AD1893, I don't need the 18.432MHz clock anymore. The SM5843 and the uDP65031 need to be fed by the 16.9MHz of CXD2545Q or TDA1315H.
Fabian
According the Japanese datasheet for the CXD2545Q, it does not have an I2S mode and the data out on pins 45,46 & 47 is in what Sony and Philips refer to as the Sony format i.e. 48bit slots per L/R pair, BCLK/SCLK fixed at 48Fs and right or LSB -justified data with data valid on the rising edge of bitclock. With that in mind and the fact that the TDA1315 is an I2S only device, it is far more likely that the logic is converting the Sony format of the CXD2545Q to I2S rather than the other way round. It would also explain why Teac chose to use the 48bit slots when the 64bit slots were also available. Using the 48bit slots means one less HC164.
The delay after the switch seems very odd indeed in that it would make the data incompatible with any of the i/o formats accepted by the AD1893.
The delay after the switch seems very odd indeed in that it would make the data incompatible with any of the i/o formats accepted by the AD1893.
Well, I don't have a datasheet of CXD2545Q, so I relied on the output description of all the CXD25** of which I found a datasheet at Sony datasheet search.
The outputs of every CXD25** are exactly as you described (48bit slots per L/R pair, BCLK/SCLK fixed at 48Fs and right or LSB -justified data with data valid on the rising edge of bitclock). This just to be sure we're talking of the same format.
The AD1893 is configured like I described in my first posting (see AD1893 datasheet p. 18, fig 24: BCLK_I normal mode, DATA IN no MSB delay mode).
I wonder why you think delaying LRCK by 8 bitcycles shouldn't work, because I can hear some nice music.
Philips I2S is converted to Sony format, I'm quite sure about this. You could hit the email button below and I'll send you the circuits if Alexander is in agreement.
You can have a look at the LRCK delay circuit at http://www.garmin.prv.pl/ -> zaplecze -> czytenlia. There you can see some more 74HC* logic between AD1893 and SM5843. Does anybody have an idea what this is for?
Fabian
P.S. Ray, are you tweaking a Teac yourself?
The outputs of every CXD25** are exactly as you described (48bit slots per L/R pair, BCLK/SCLK fixed at 48Fs and right or LSB -justified data with data valid on the rising edge of bitclock). This just to be sure we're talking of the same format.
The AD1893 is configured like I described in my first posting (see AD1893 datasheet p. 18, fig 24: BCLK_I normal mode, DATA IN no MSB delay mode).
I wonder why you think delaying LRCK by 8 bitcycles shouldn't work, because I can hear some nice music.
Philips I2S is converted to Sony format, I'm quite sure about this. You could hit the email button below and I'll send you the circuits if Alexander is in agreement.
You can have a look at the LRCK delay circuit at http://www.garmin.prv.pl/ -> zaplecze -> czytenlia. There you can see some more 74HC* logic between AD1893 and SM5843. Does anybody have an idea what this is for?
Fabian
P.S. Ray, are you tweaking a Teac yourself?
6?¬6?!?buy this finetuned digital converter upgrade for Teac VRDS-25 in e-bay:
http://cgi.ebay.de/ws/eBayISAPI.dll?ViewItem&category=11383&item=3477687931&rd=1&ssPageName=WDVW
"Austauschplatine für den werksseitig implementierten low-cost AD1893 Sample Rate Converter. Pinkkompatible Adapterplatine mit dem high-performance AD1896 Converter IC. Kompromisslose Ausführung mit Black Gate NX Kondensatoren. Es muß lediglich der AD1893 ausgelötet werden und die Adapterplatine eingelötet werden."
http://cgi.ebay.de/ws/eBayISAPI.dll?ViewItem&category=11383&item=3477687931&rd=1&ssPageName=WDVW
"Austauschplatine für den werksseitig implementierten low-cost AD1893 Sample Rate Converter. Pinkkompatible Adapterplatine mit dem high-performance AD1896 Converter IC. Kompromisslose Ausführung mit Black Gate NX Kondensatoren. Es muß lediglich der AD1893 ausgelötet werden und die Adapterplatine eingelötet werden."
There is the possiblity of getting a VRDS-25? but I am not absolutely sure it is a 25x.
Anyway back to the what the logic does. Not that it matters much as it obviously works, its just a matter of what to call it but the mode pins on the AD1893 are set to Left justified data and that rules out the Sony format which is right justified.
The logic between the AD1893 and the SM5843 generates BCLK/SCLK and LRCLK at the new samplerate. That is how the AD1893 knows what samplerate to convert the incoming data to.
ray.
Anyway back to the what the logic does. Not that it matters much as it obviously works, its just a matter of what to call it but the mode pins on the AD1893 are set to Left justified data and that rules out the Sony format which is right justified.
The logic between the AD1893 and the SM5843 generates BCLK/SCLK and LRCLK at the new samplerate. That is how the AD1893 knows what samplerate to convert the incoming data to.
ray.
The modules I mentioned where the ones Worboren has linked to in his post above. They are produced by www.audiotuning.de.
I've read on this forum that someone did direct comparison between a setup with and without AD1896. The one without ASRC was preferred. That's why I'll first try to use no ASRC at all (and it's cheaper).
I've already made the digital filter characteristc of the SM5843 switchable. Slow roll off mode sounds much better.
Fabian
I've read on this forum that someone did direct comparison between a setup with and without AD1896. The one without ASRC was preferred. That's why I'll first try to use no ASRC at all (and it's cheaper).
I've already made the digital filter characteristc of the SM5843 switchable. Slow roll off mode sounds much better.
Fabian
Removing AD1893
Hello,
As I see it the 74HC164 and the 74HC74 are used to delay the LR clock by 8 bitclockcycles so converting the Sony format to the MSB first format the AD1893 likes to see.
What only confuses me is that the 74HC74 is using the inverted bitclock as clock, and the 74HC164 not.
Now you want to remove the AD1893. Then you should ask yourselve what kind of mode the SM5843 likes to see. I dunno, but this could be unriddled from the AD1893 ouput mode settings or from the SM5843 datasheet.
I think you then can use the 16.9344 MHz clock for the digital filter.
Personally I would retain the AD1893 and delete the SM5843 digital filter as the ASR already contains a digital filter.
I find it at least curious audiotuning.de is offering three AD1896 modification prints on Ebay but is silent about this on their website.
Hello,
As I see it the 74HC164 and the 74HC74 are used to delay the LR clock by 8 bitclockcycles so converting the Sony format to the MSB first format the AD1893 likes to see.
What only confuses me is that the 74HC74 is using the inverted bitclock as clock, and the 74HC164 not.
Now you want to remove the AD1893. Then you should ask yourselve what kind of mode the SM5843 likes to see. I dunno, but this could be unriddled from the AD1893 ouput mode settings or from the SM5843 datasheet.
I think you then can use the 16.9344 MHz clock for the digital filter.
Personally I would retain the AD1893 and delete the SM5843 digital filter as the ASR already contains a digital filter.
I find it at least curious audiotuning.de is offering three AD1896 modification prints on Ebay but is silent about this on their website.
Thanks for your input Elso. It is indeed a bit “suspicious” that audiotuning doesn’t mention this replacement modules on their webpage.
After looking at all the input and output modes supported by AD1893 and SM5843, it’s probably easier to remove AD1893 than SM5843. AD1893 supports only serial data output, but uPD65031 would need parallel data. Another advantage would be that I could set SM5843 to accept sony’s format that is already available in the Teac.
I’ll lose the jitter rejection capability, which can be advantageous when using the Teac as a DAC only, but I’ll gain by omitting a digital filter. I’ll keep in SM5843 as it is said to be very good.
I’m not sure about the bitclock feeding 74HC164 or 74HC74 (I’ve just read their datasheets for the first time, yes I’m a bloody newbie). Luckily I can omit that bit clock shifting circuit when removing AD1893.
If I go with SM5843, I’ll have to switch 16.9344MHz clock coming from CXD2545Q or TDA1315H. I guess this clock must be synchronous to BCK/LRCK/DATA.
Can I just switch it similar to how it’s already done with BCK/LRCK/DATA. These tree lines are switched with a 74HC4053.
Fabian
After looking at all the input and output modes supported by AD1893 and SM5843, it’s probably easier to remove AD1893 than SM5843. AD1893 supports only serial data output, but uPD65031 would need parallel data. Another advantage would be that I could set SM5843 to accept sony’s format that is already available in the Teac.
I’ll lose the jitter rejection capability, which can be advantageous when using the Teac as a DAC only, but I’ll gain by omitting a digital filter. I’ll keep in SM5843 as it is said to be very good.
I’m not sure about the bitclock feeding 74HC164 or 74HC74 (I’ve just read their datasheets for the first time, yes I’m a bloody newbie). Luckily I can omit that bit clock shifting circuit when removing AD1893.
If I go with SM5843, I’ll have to switch 16.9344MHz clock coming from CXD2545Q or TDA1315H. I guess this clock must be synchronous to BCK/LRCK/DATA.
Can I just switch it similar to how it’s already done with BCK/LRCK/DATA. These tree lines are switched with a 74HC4053.
Fabian
Fabian,
In your position the only changes I would make are these.
1.Remove the AD1893 and link BCLKI to BCLKO, LRCLKI to LRCLKO and DATAI to DATAO.
2.Remove the resistors at the output of U104A & B and power down all the logic associated with the 18.432MHz clock except for U105A & B where I'd remove the crystal and ground the inputs.
3. Cut the track to the XTI input of the SM5843A at a convinient point close to the XTI pin and connect the the 384Fs clock that drives the TDA1315 and the CXD2545.
ray.
In your position the only changes I would make are these.
1.Remove the AD1893 and link BCLKI to BCLKO, LRCLKI to LRCLKO and DATAI to DATAO.
2.Remove the resistors at the output of U104A & B and power down all the logic associated with the 18.432MHz clock except for U105A & B where I'd remove the crystal and ground the inputs.
3. Cut the track to the XTI input of the SM5843A at a convinient point close to the XTI pin and connect the the 384Fs clock that drives the TDA1315 and the CXD2545.
ray.
Ray,
Concerning the the SM5843, I'll first try your solution. If it works, I'll be happy. If it doesn't work, I still can remove U105, U106 and U107 and change the input mode of SM5843.
But I think it's not possible to directly connect the 16.9344MHz signal between CXD2545Q, TDA1315H and SM5843. CXD2545Q has a 16.9344MHz input, but TDA1535H has a 16.9344MHz output when used as SPDIF reciever. When SPDIF signal is disconnected, frequency will drift to 19MHz (says the datasheet).
There's probably no other way than implementing a switch, if I want to use the digital inputs as well.
Fabian
Concerning the the SM5843, I'll first try your solution. If it works, I'll be happy. If it doesn't work, I still can remove U105, U106 and U107 and change the input mode of SM5843.
But I think it's not possible to directly connect the 16.9344MHz signal between CXD2545Q, TDA1315H and SM5843. CXD2545Q has a 16.9344MHz input, but TDA1535H has a 16.9344MHz output when used as SPDIF reciever. When SPDIF signal is disconnected, frequency will drift to 19MHz (says the datasheet).
There's probably no other way than implementing a switch, if I want to use the digital inputs as well.
Fabian
It works!
Hi all,
I just removed AD1893 as described above. The 16.9344MHz clock comes from Pin63 at CXD2545Q. Digital out works, digital in not yet.
Before I removed AD1893 I tried to trim all four D/A converter chips (AD1862) for lowest low level distortion as described in the datasheet. I couldn't measure any distortions because the noise floor was at abaut -92dB. I could hardly identify a -80dB signal on my screen. Not very good for such an expensive CD player. Without AD1893 noise performance is at least 20dB better. So I was able to adjust every AD1862 (but there is only very small improvement).
Now its time for some listening...
Fabian
Hi all,
I just removed AD1893 as described above. The 16.9344MHz clock comes from Pin63 at CXD2545Q. Digital out works, digital in not yet.
Before I removed AD1893 I tried to trim all four D/A converter chips (AD1862) for lowest low level distortion as described in the datasheet. I couldn't measure any distortions because the noise floor was at abaut -92dB. I could hardly identify a -80dB signal on my screen. Not very good for such an expensive CD player. Without AD1893 noise performance is at least 20dB better. So I was able to adjust every AD1862 (but there is only very small improvement).
Now its time for some listening...
Fabian
Everything works now
Hi,
today, some weeks after starting this tuning adventure, I’ve come to a successful end.
After removing AD1893 as described in the posts above, I’ve set SM5843 into the mode where it directly accepts BCK, LRCK and DATA coming from CXD2545Q. This works very well, no glue logic (except switching circuit) is required between decoder and digital filter. Some minor distortions disappeared. But I have no idea how distortion performance is influenced by those 74HC**.
To make the signals provided by the digital input receiver compatible with the digital filter, I had to delay DATA by another 8 bitclock cycles. This is necessary because of the different word frame length of TDA1315H (32 bitclock cycles) and CXD2545Q (24 bitclock cycles).
Then there was a problem with the 16.9344MHz that must be switched. I’ve copied the switching circuit of BCK, LRCK and DATA which works well. And I’ve installed a TentXO which feeds the decoder and the digital filter. When connecting an external transport, there’s no benefit of precise clock and the difference in sound quality is apparent.
The output format of the SM5843 remains unchanged. I’ve omitted UPD65031 as well and settled for balanced D/A conversion by inverting one DATA line for each channel.
UPD65031 did some kind of signal conversion, maybe something similar to what is implemented in PCM1702 or PCM1704. Once I measured the output of one AD1862 (with UPD65031 still in its place). It measured perfectly even at low levels, but at signal levels higher than –1dB, even order harmonics increased to a very high niveau of about –35dB. There were no odd order harmonics at all. I guess the difference amp that followed the I/V stage has cancelled all even order harmonics.
Without UPD65031 guaranteeing low low level distortions, I adjusted every AD1862 as recommended in the datasheet. It’s great to see disappearing every distortion peak below the noise floor when adjusting the trim potis. With UPD65031 in its place trimming of AD1862 was actually useless.
For I/V and buffer I still use the original OPA2132 and NJM2114L. There’s no analog filter till now.
Of course I’ve added some Panasonic FCs, Oscons, small 100n Wimas and Micas. Output resistance is 75 Ohm, full scale output swing is +/- 3.5V.
I've attached a picture, because I know everybody likes to see pics
Fabian
Hi,
today, some weeks after starting this tuning adventure, I’ve come to a successful end.
After removing AD1893 as described in the posts above, I’ve set SM5843 into the mode where it directly accepts BCK, LRCK and DATA coming from CXD2545Q. This works very well, no glue logic (except switching circuit) is required between decoder and digital filter. Some minor distortions disappeared. But I have no idea how distortion performance is influenced by those 74HC**.
To make the signals provided by the digital input receiver compatible with the digital filter, I had to delay DATA by another 8 bitclock cycles. This is necessary because of the different word frame length of TDA1315H (32 bitclock cycles) and CXD2545Q (24 bitclock cycles).
Then there was a problem with the 16.9344MHz that must be switched. I’ve copied the switching circuit of BCK, LRCK and DATA which works well. And I’ve installed a TentXO which feeds the decoder and the digital filter. When connecting an external transport, there’s no benefit of precise clock and the difference in sound quality is apparent.
The output format of the SM5843 remains unchanged. I’ve omitted UPD65031 as well and settled for balanced D/A conversion by inverting one DATA line for each channel.
UPD65031 did some kind of signal conversion, maybe something similar to what is implemented in PCM1702 or PCM1704. Once I measured the output of one AD1862 (with UPD65031 still in its place). It measured perfectly even at low levels, but at signal levels higher than –1dB, even order harmonics increased to a very high niveau of about –35dB. There were no odd order harmonics at all. I guess the difference amp that followed the I/V stage has cancelled all even order harmonics.
Without UPD65031 guaranteeing low low level distortions, I adjusted every AD1862 as recommended in the datasheet. It’s great to see disappearing every distortion peak below the noise floor when adjusting the trim potis. With UPD65031 in its place trimming of AD1862 was actually useless.
For I/V and buffer I still use the original OPA2132 and NJM2114L. There’s no analog filter till now.
Of course I’ve added some Panasonic FCs, Oscons, small 100n Wimas and Micas. Output resistance is 75 Ohm, full scale output swing is +/- 3.5V.
I've attached a picture, because I know everybody likes to see pics
Fabian
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