I hope I dare to buy a Sony PCM machine like 3348 etc.... which is about 4500 usd, not too expensive compare to its original price but I worry I cannot have the knowledge to keep it running! Actually I am looking for a good DAT so that I do not need to make another V4 or V5 etc..... So now I am searching for pro-audio gears to replace consumer gears.... 
Finney,
You might be surprised - but I'm totally with You on this point! It's a thin line - though please, don't forget that it's not a commercial product, and I'm not a TI engineer,
, so I don't have to take into account the needs of recording studios etc.
Such a "loose loop" plus a VCXO solution is clearly problematic for professional mass production. John Westlake already had written at diyhifi, that he understands why Lavry [probably] dropped the Crystal Lock from the DA10. Not because it does not work / sound well - but because it might not lock, drop out of lock etc. John Swenson was warning about the same recently.
The first thing I had written to Paul was a list of these risks.
But. It works / serves blamelessly since a year at my house. And I feel I can have this trade of some risk in exchange for the quality.
Yes it's picky about it's partnering equipment. A diyer can always tune a bit the clock in his Cd player, though laptops are nasty beasts..
Ciao, George
You might be surprised - but I'm totally with You on this point! It's a thin line - though please, don't forget that it's not a commercial product, and I'm not a TI engineer,
, so I don't have to take into account the needs of recording studios etc. Such a "loose loop" plus a VCXO solution is clearly problematic for professional mass production. John Westlake already had written at diyhifi, that he understands why Lavry [probably] dropped the Crystal Lock from the DA10. Not because it does not work / sound well - but because it might not lock, drop out of lock etc. John Swenson was warning about the same recently.
The first thing I had written to Paul was a list of these risks.
But. It works / serves blamelessly since a year at my house. And I feel I can have this trade of some risk in exchange for the quality.
Yes it's picky about it's partnering equipment. A diyer can always tune a bit the clock in his Cd player, though laptops are nasty beasts..
Ciao, George
Joseph K said:
You might be surprised - but I'm totally with You on this point! It's a thin line - though please, don't forget that it's not a commercial product, and I'm not a TI engineer,
Such a "loose loop" plus a VCXO solution is clearly problematic for professional mass production. John Westlake already had written at diyhifi, that he understands why Lavry [probably] dropped the Crystal Lock from the DA10. Not because it does not work / sound well - but because it might not lock, drop out of lock etc. John Swenson was warning about the same recently.
The first thing I had written to Paul was a list of these risks.
But. It works / serves blamelessly since a year at my house. And I feel I can have this trade of some risk in exchange for the quality.
Yes it's picky about it's partnering equipment. A diyer can always tune a bit the clock in his Cd player, though laptops are nasty beasts..
Ciao, George
I knew from post 1 exactly what you had done and I am honestly to say that I am deeply impressed. This is not easy even for a good engineer to do. The problem is that we have so many people at this forum talking about so many different things which make the ideas hard to get through clearly. Anyway, no biggie.
Please dont talk about anything related to TI again. I am afraid that I have talked too much. I have a generic NDA with TI and this can kill me.
Joseph K said:
George, Finney
I'm still suffering my cold but, decided to turn off MPLAB SIM and work out what I was doing wrong. I've spent the best part of the morning thinking about what was going on and now I think I have fixed the issue
I now have to kick my girlfriend off her laptop so I can program the chip - the joys of running a mac!!I wasn't dealing with the 2's complement math correctly, just adding to the previous output which meant I was seeing a lot of overflows and wrap around. Once clicked to what was happening I realised this is the source of my troubles, and have just finished rewriting the code to keep the all the math in 2's complement. I'm now only converting the result to unsigned binary to send to the DAC. I haven't tested the new code "in the wild" but the output is looking far more sane in MPLAB Sim so I think this is a major step in the right direction.
cheers
Paul
KWAK’s Asynchronous Reclocker-3
To All,
Here are some remarks on KWAK’s Asynchronous Reclocker-3, written by Herbert Reith on the German diy forum “Audiomap”:
http://www.audiomap.de/forum/index....id=21787&sid=45c50f883a83ab7785f08e54ade68c32
This surely correspond with all the above mentioned info and the Lavri papers:
"In principle, one should ensure with such a circuit, that all the signals at the exit remain in very firm and stable relations to the Takt. (however) much that one sees and read over Reclocking is - cautiously expressed - quetionable.
If a circuit takes over a signal with a clock, the signal which can be taken over should be always stable around the active flank - thus either 0 or 1. If this is not the case, then no point in starting working with the signal.
Depending upon logic, it can internally come to a situation, where this signals quasi swings. It can also be that the internal logic needs 3-5 times so long, until it gets to a stable condition. With some logic families these meta-stable conditions are defined in the Documents, with others it is not so.
If one puts now whichever digital signal at the entrance of a flip-flop, and then supplies the thing with whichever clock, then one will recognize very clear, jumps in the signal at the exit. The signal at the exit will be mostly of clocks long 0 or 1, however sometimes evenly also values between them. Those are then the evidences of that times at which the input signal was not stable around the active clock’s flanks.
Partly one tries to overcome this problem by connecting a further flip-flop stage, at the outlet side. At their exit the signals are then hopefully again in a firm alliance to the clock - however the signals now are about + - 1 cycle-length of difference to the origin!
If you e.g. take this circuit and simply insert it - as it is – in between the I2S-Signale, then you are gotten exactly the above described effects!
Generally, with an interface like the I2S, all signals must have certain Timing in relation to the bit (Takt). The receiver reads the signals with the related-to-it clock and has thereby exactly the problems which were described above. If the signals are not perfectly stable around the active flank, then it can come e.g. at the converter to the fact that it converts wrong data. A further problem is that the serially read of data must be spent sometime in a firm time slot pattern. That is made dependent on the WordClock. If that varies now, then this can mean jitter at the exit.
Some converters have also internal a digital filter or other stages and clocks thus everything with the BitClock. Then a jitter arose, if varies
To go simply into the I2S-Signale and to switch there a Reclocking-Circuit, would be very likely an error and a jitter machine. If one makes that by himself, and if it costs him much work, possibly also much money - then that will naturally sounds excellent. Objectively it is however a shot in Knee.
A really functioning Reclocking circuit must know exactly, with whom it has to co-operate, likewise supply, transmit and receive the signals to/from. It must works in any case with a Takt, which is as stable as possible and has a firm relationship to all signals. Then and only then, signals at the exit of the circuit, have fewer fluctuations as at the entrance. Whether the circuit play here a role or not, depends on the circuit itself.
In an application made of SPDIF-Receiver, the digital filter and converter bases their work in the long run in referring to the clock which must be reconstructed from the SPDIF input data;
That is thus that which is supplied by the receiver component.
A simple synchronising-arround is so not possible. If this is wished, then one must heavily calculate; this is done by the SRC circuit.
Other try is consists of adjusting a new highly-exact Takt (based on the Takt of the receiver) in such a way, that it can adjusts/compensate the rather brief fluctuations of the receiver’s takt but follows it exactly in the Timings. Whether the average DIY can realize such a low-jitter circuit in the way like that the receiver component anyhow does, without sufficient experience and appropriate measuring instruments, that is much to be doubted."
AND:
"If the clock of the circuit is not exact multiple of the signal clock rate and/or it is not linked with this phase-star, the circuit will increase the jitter in any case clearly. With 100MHz the Takt- length amounts are of 10ns. The output signal exhibits thus “jumps” of min. 10ns.
A very good receiver generates a clock with fluctuations of 200ps. The Reclocker with 100MHz makes the jitters thus around at least the factor of 50 worsens.
But how much one needs? With 16 bit and 44.1 KHz, a signal distortion of 1 LSB corresponds in approximately a time of 350ps. Or in the opposite way, - a jitter of under 350ps goes down, regarding quantization noise; a larger causes a reduction of the accuracy.
The 10ns specified above corresponds to about 28 LSBs. A 44.1 KHz raster has about 2300 10ns-Fenster “fitted in”, which corresponds to an effective dissolution of 11bit.
Jitter is a signal distortion, just as rattles/clinks, intermodulation noise…. It is quite possible that it sounds better with more jitters than without…. there are also people who insist on having 10% rattle /clink / distortion ... ".
IJ.
To All,
Here are some remarks on KWAK’s Asynchronous Reclocker-3, written by Herbert Reith on the German diy forum “Audiomap”:
http://www.audiomap.de/forum/index....id=21787&sid=45c50f883a83ab7785f08e54ade68c32
This surely correspond with all the above mentioned info and the Lavri papers:
"In principle, one should ensure with such a circuit, that all the signals at the exit remain in very firm and stable relations to the Takt. (however) much that one sees and read over Reclocking is - cautiously expressed - quetionable.
If a circuit takes over a signal with a clock, the signal which can be taken over should be always stable around the active flank - thus either 0 or 1. If this is not the case, then no point in starting working with the signal.
Depending upon logic, it can internally come to a situation, where this signals quasi swings. It can also be that the internal logic needs 3-5 times so long, until it gets to a stable condition. With some logic families these meta-stable conditions are defined in the Documents, with others it is not so.
If one puts now whichever digital signal at the entrance of a flip-flop, and then supplies the thing with whichever clock, then one will recognize very clear, jumps in the signal at the exit. The signal at the exit will be mostly of clocks long 0 or 1, however sometimes evenly also values between them. Those are then the evidences of that times at which the input signal was not stable around the active clock’s flanks.
Partly one tries to overcome this problem by connecting a further flip-flop stage, at the outlet side. At their exit the signals are then hopefully again in a firm alliance to the clock - however the signals now are about + - 1 cycle-length of difference to the origin!
If you e.g. take this circuit and simply insert it - as it is – in between the I2S-Signale, then you are gotten exactly the above described effects!
Generally, with an interface like the I2S, all signals must have certain Timing in relation to the bit (Takt). The receiver reads the signals with the related-to-it clock and has thereby exactly the problems which were described above. If the signals are not perfectly stable around the active flank, then it can come e.g. at the converter to the fact that it converts wrong data. A further problem is that the serially read of data must be spent sometime in a firm time slot pattern. That is made dependent on the WordClock. If that varies now, then this can mean jitter at the exit.
Some converters have also internal a digital filter or other stages and clocks thus everything with the BitClock. Then a jitter arose, if varies
To go simply into the I2S-Signale and to switch there a Reclocking-Circuit, would be very likely an error and a jitter machine. If one makes that by himself, and if it costs him much work, possibly also much money - then that will naturally sounds excellent. Objectively it is however a shot in Knee.
A really functioning Reclocking circuit must know exactly, with whom it has to co-operate, likewise supply, transmit and receive the signals to/from. It must works in any case with a Takt, which is as stable as possible and has a firm relationship to all signals. Then and only then, signals at the exit of the circuit, have fewer fluctuations as at the entrance. Whether the circuit play here a role or not, depends on the circuit itself.
In an application made of SPDIF-Receiver, the digital filter and converter bases their work in the long run in referring to the clock which must be reconstructed from the SPDIF input data;
That is thus that which is supplied by the receiver component.
A simple synchronising-arround is so not possible. If this is wished, then one must heavily calculate; this is done by the SRC circuit.
Other try is consists of adjusting a new highly-exact Takt (based on the Takt of the receiver) in such a way, that it can adjusts/compensate the rather brief fluctuations of the receiver’s takt but follows it exactly in the Timings. Whether the average DIY can realize such a low-jitter circuit in the way like that the receiver component anyhow does, without sufficient experience and appropriate measuring instruments, that is much to be doubted."
AND:
"If the clock of the circuit is not exact multiple of the signal clock rate and/or it is not linked with this phase-star, the circuit will increase the jitter in any case clearly. With 100MHz the Takt- length amounts are of 10ns. The output signal exhibits thus “jumps” of min. 10ns.
A very good receiver generates a clock with fluctuations of 200ps. The Reclocker with 100MHz makes the jitters thus around at least the factor of 50 worsens.
But how much one needs? With 16 bit and 44.1 KHz, a signal distortion of 1 LSB corresponds in approximately a time of 350ps. Or in the opposite way, - a jitter of under 350ps goes down, regarding quantization noise; a larger causes a reduction of the accuracy.
The 10ns specified above corresponds to about 28 LSBs. A 44.1 KHz raster has about 2300 10ns-Fenster “fitted in”, which corresponds to an effective dissolution of 11bit.
Jitter is a signal distortion, just as rattles/clinks, intermodulation noise…. It is quite possible that it sounds better with more jitters than without…. there are also people who insist on having 10% rattle /clink / distortion ... ".
IJ.
PA0SU said:
Please, next time before you start the bragging again, at least do some math first. 10us jitter? Let's see. DAT can do 16bit/48KHz. 1 second /48K = 21us. 21us covers 16 x 2 = 32bit so each bit cycle is 656ns. This even does not include the lead/postfix track data.
Now 10us jitter covers 10/0.656 = 15 bit cycles. I am wondering how a DAT machine will ever work with a 10us jitter?
PCM63 LATCH has a 3ps jitter? What latch are you talking about? Where, when? And how did you measure it? What makes you come to this conclusion? I am sure TI/BB engineers will be really eager to know. Probably just another good laugh for us under the grape vine?
Re: KWAK’s Asynchronous Reclocker-3
Yep yep, most reclocking schemes are simply bogus and will not work 100% of the time. Yet dont be so discouraged because people in the communication work are dealing with similar problems all the time. You just need the right knowledges to do the work.
The major challenge of I2S is the transmission of the clock signal. However, even a 25MHz signal running a 30cm distance isnt that big a deal. Remember that there are instruements which can measure jitter down to 1ps/rms? They can do this with a cable connected probe! Again, you will just have to do it right.
irgendjemand said:
Yep yep, most reclocking schemes are simply bogus and will not work 100% of the time. Yet dont be so discouraged because people in the communication work are dealing with similar problems all the time. You just need the right knowledges to do the work.
The major challenge of I2S is the transmission of the clock signal. However, even a 25MHz signal running a 30cm distance isnt that big a deal. Remember that there are instruements which can measure jitter down to 1ps/rms? They can do this with a cable connected probe! Again, you will just have to do it right.
Herb,
I may be a dreamer some times but most of the time I sit down and try something with my hands and ears to confirm what I think.
I also use my brain to judge and I believe DAT is good as they are widely used in Boardcasting and Professional arean. This is just common sense to me.
Spencer
I may be a dreamer some times but most of the time I sit down and try something with my hands and ears to confirm what I think.
I also use my brain to judge and I believe DAT is good as they are widely used in Boardcasting and Professional arean. This is just common sense to me.
Spencer
Re: KWAK’s Asynchronous Reclocker-3
Remember, Remember, REMEMBER: Asynchronous Reclocking is absolutely RUBBISH.
For the present logic all digital audio is that slow so that the logic is always fast enough. In our applications ( 8x OS, 256Fs) the LATCH- block (at the entrance of the PCM63) has a frequency of 8 x 44.1 kHz = 353 kHz which means that the block-length is about 1.5 us (1.5 micro seconds) The flanks of 74HC.... logic are about 6 ns (nano seconds). This means that the flanks of the LATCH take 1/100 of the time of the LATCH-block. Should it not be possible to hit that block which is 99% of the time 0 (zero) or 1 (one) with a clock signal? I think this is peanuts.
Of cource you should examine if the clock comes somewhere in the middle of the LATCH-block. For this you need an oscilloscope......
Above is the aswer.... no problem at all.
Concoctions!
Here the stable situation is about 90%, so.... I do not see any problem.
Therefore, in 'DACprincipe4' I take the (low jitter) clock from the transport (no VCXO, no other oscillator, nothing) to assure this relationship: SYNCHRONE reclocking!
Not with my 'DACprincipe4': the clock output of the receiver is left alone!!!!
SRC ? Help me?
For this a VCXO is to be used (if you do not want to take the clock from the transport).
A VCXO is no more and no less then an analog band pass filter with a band width of two times the cut off frequency of the PLL-circuit in it (as long as the oscillator itself is a low-noise one!)
Sure, sure, sure !!!! Asynchronous reclocking is a fallacy.
Here we are: I can not argue it, but when you LISTEN, a jitter on the clock signal of, say, 3 ps can very well be distinguished from one with 10 ps. Do not ask me why, but many experiances here with the EDDC has clearly prooved it. I will show you if you are in Eindhoven.
I do not agree! For the perseption it is different. Jitter is in another dimension.
irgendjemand said:
Remember, Remember, REMEMBER: Asynchronous Reclocking is absolutely RUBBISH.
For the present logic all digital audio is that slow so that the logic is always fast enough. In our applications ( 8x OS, 256Fs) the LATCH- block (at the entrance of the PCM63) has a frequency of 8 x 44.1 kHz = 353 kHz which means that the block-length is about 1.5 us (1.5 micro seconds) The flanks of 74HC.... logic are about 6 ns (nano seconds). This means that the flanks of the LATCH take 1/100 of the time of the LATCH-block. Should it not be possible to hit that block which is 99% of the time 0 (zero) or 1 (one) with a clock signal? I think this is peanuts.
Of cource you should examine if the clock comes somewhere in the middle of the LATCH-block. For this you need an oscilloscope......
Above is the aswer.... no problem at all.
Concoctions!
Here the stable situation is about 90%, so.... I do not see any problem.
Therefore, in 'DACprincipe4' I take the (low jitter) clock from the transport (no VCXO, no other oscillator, nothing) to assure this relationship: SYNCHRONE reclocking!
Not with my 'DACprincipe4': the clock output of the receiver is left alone!!!!
SRC ? Help me?
For this a VCXO is to be used (if you do not want to take the clock from the transport).
A VCXO is no more and no less then an analog band pass filter with a band width of two times the cut off frequency of the PLL-circuit in it (as long as the oscillator itself is a low-noise one!)
Sure, sure, sure !!!! Asynchronous reclocking is a fallacy.
Here we are: I can not argue it, but when you LISTEN, a jitter on the clock signal of, say, 3 ps can very well be distinguished from one with 10 ps. Do not ask me why, but many experiances here with the EDDC has clearly prooved it. I will show you if you are in Eindhoven.
I do not agree! For the perseption it is different. Jitter is in another dimension.
PA0SU said:
Well, you were yelling "micro second" originally then how conveniently you switched from "micro second" to "nano second" by calling it a mistake? And you are calling this with a guy who's dealing with "femto second" all the time?
The fact is that it's even not 10ns. Want to keep guessing? Haha. 10ns jitter? Those widely used DDS computer backup systems will have serious reliability problem already. Not even mention DDS4, DAT72, and DAT160 systems.
The beauty of the helix drum is the output is very similar to what a correctly working Lavry's circuit is supposed to do. This is all about high moving mass and moving momentum. No way to duplicate this feat with a laser head controlled by constantly vibrating servo.
PCM63 latch time is a wrong way to call the situation you tried to explain. You can say that the signals reach PCM63 with a 3ps jitter or the clock input has 3ps jitter. PCM63 latch? What's that? The time when PCM63's input buffer latches inputs? I dont think non-chip designer can ever measure it.
Anyway. I assume you use Tent's XO? Let's see... Tent's fixed frequency XO is bascially a mediocre 3ps/rms jitter XO. I doubt the VCXO will be any better. With extra compoments added in, you claim that your PLL loop has a 3ps performance? Well, it's possible that if you start with a 0.18ps/rms XO then package the whole thing in a small IC package, but a PLL loop in board with a 3ps XO? Not even mention the jitter performance when real active SPDIF signal starts to come in.
Finney,
I am sure that Herb will response ... meanwhile I can tell you that at least in 2 major points, you might have well missed his all work
.
First of all, Herb wrote on this thread (Post #161): "I do NOT use a VCXO with PLL or so. I route the clock signal in my cd-player directly to the DAC.....". Then, in Post #176 he wrote: “For all certainty: VCXO's always produce more noise/jitter than XO's”. He is taking the XO from the Transport - see also his “DAC Principia 4”. He is telling us all this since long..
And: The RMS/Jitter of his Rutgers Oscillator is 0.4060 ps. ... Just read his mails..
The other point you missed – just like you wrote here, Herb implies that it is all about moving mass & momentum… In other words, this perfectly corresponds with his explanation for his using of the Philips CD 624 – as he explained - because of the low-mass laser-head, etc. ….
As for the PCM63’s LATCH: As much as I understood from Herb, the all problem arise also because there is no ideal isolation of the LATCH from its data and other clock signals - inside the PCM63 (!!!!!). Therefore, the idea of the "DAC Principia 4" is the re-clocking of the data and the clock to the DAC as well. Well, this can’t be so bad..
I am sure many here whould be happy to have the mentioned 3ps!
Greetings,
IJ
I am sure that Herb will response ... meanwhile I can tell you that at least in 2 major points, you might have well missed his all work
.First of all, Herb wrote on this thread (Post #161): "I do NOT use a VCXO with PLL or so. I route the clock signal in my cd-player directly to the DAC.....". Then, in Post #176 he wrote: “For all certainty: VCXO's always produce more noise/jitter than XO's”. He is taking the XO from the Transport - see also his “DAC Principia 4”. He is telling us all this since long.
.And: The RMS/Jitter of his Rutgers Oscillator is 0.4060 ps. ... Just read his mails.
.The other point you missed – just like you wrote here, Herb implies that it is all about moving mass & momentum… In other words, this perfectly corresponds with his explanation for his using of the Philips CD 624 – as he explained - because of the low-mass laser-head, etc. …
.As for the PCM63’s LATCH: As much as I understood from Herb, the all problem arise also because there is no ideal isolation of the LATCH from its data and other clock signals - inside the PCM63 (!!!!!). Therefore, the idea of the "DAC Principia 4" is the re-clocking of the data and the clock to the DAC as well. Well, this can’t be so bad.
.I am sure many here whould be happy to have the mentioned 3ps!
Greetings,
IJ
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