Re: Phillips CD
If you find one in near-mint conditions (for a fair price) just let me know, I will probably be interested.. the only problem would be ho to send you the money.. last time I bought something from Poland (pcbs from xsnailx) bank expenses nearly killed me!
A Paypal account is highly suggested...
Cheers
Andrea
zygibajt said:
If you find one in near-mint conditions (for a fair price) just let me know, I will probably be interested.. the only problem would be ho to send you the money.. last time I bought something from Poland (pcbs from xsnailx) bank expenses nearly killed me!
A Paypal account is highly suggested...
Cheers
Andrea
Re: Re: Phillips CD
Andrea,
Since january 2002, bank transfers cost much less inside the euro zone
I paid 3€ for a transfer to germany
Andypairo said:
If you find one in near-mint conditions (for a fair price) just let me know, I will probably be interested.. the only problem would be ho to send you the money.. last time I bought something from Poland (pcbs from xsnailx) bank expenses nearly killed me!
A Paypal account is highly suggested...
Cheers
Andrea
Andrea,
Since january 2002, bank transfers cost much less inside the euro zone
I paid 3€ for a transfer to germany
I see them (930/931 950/951) quite often.If it's working it usually cost about 70-80 Euro.But more often there are available with dead laser lens (for some 15-25 Euro).Once I even bought one 950 but I had to pay almost 100Euro for a new laser and I gave up and sold it as broken.
But the question is (Jean-Paul please answer if you can): are they really worth the effort modifying them.I would probably go for some with TDA 1541 chip.
Also Jean Paul could you please tell me what would be the killer old Phillips/Marantz Cd Player to modify?
I know Elso says that they are too old and I won't get the laser when it dies,but this is not a big deal for me becouse I can buy some old Phillips with working CDM 1 or CDM4 drive almost any time I want for some little money (especialy one model that I see very often,I dont remember the number but It was suppose to be the first CD player Phillips released,and they always work).
So if You (Jean - Paul) could name a few old ,killer to modify cd-s that would be nice.
Bartek
But the question is (Jean-Paul please answer if you can): are they really worth the effort modifying them.I would probably go for some with TDA 1541 chip.
Also Jean Paul could you please tell me what would be the killer old Phillips/Marantz Cd Player to modify?
I know Elso says that they are too old and I won't get the laser when it dies,but this is not a big deal for me becouse I can buy some old Phillips with working CDM 1 or CDM4 drive almost any time I want for some little money (especialy one model that I see very often,I dont remember the number but It was suppose to be the first CD player Phillips released,and they always work).
So if You (Jean - Paul) could name a few old ,killer to modify cd-s that would be nice.
Bartek
Re: I2S Direct
Hi,
Hhere is the schematic I am currently using.
Three 50 Ohm coax cables are used between the CD-player and the DAC. Connectors should be 50 Ohm too. 0.1 µF Bypass caps on the logic IC and on all the transistors are not shown for clarity as well as ground and supply connection on the 74HC125.
The 51 Ohm resistors double as emittorresistors for the transistors as well as proper termination of the coax cable.
Scope shows clean waveforms for all three signals which can not be said for direct logic drive of simple unshielded leads.
Elso Kwak said:
Please note I use the player only as a transport or source of I2S signals.
Hi,
Hhere is the schematic I am currently using.
Three 50 Ohm coax cables are used between the CD-player and the DAC. Connectors should be 50 Ohm too. 0.1 µF Bypass caps on the logic IC and on all the transistors are not shown for clarity as well as ground and supply connection on the 74HC125.
The 51 Ohm resistors double as emittorresistors for the transistors as well as proper termination of the coax cable.
Scope shows clean waveforms for all three signals which can not be said for direct logic drive of simple unshielded leads.
Attachments
I2S Direct
Hi Andrea,
Great you got these players!
Of course 75 Ohm coax cables can also be used. In this case use 75 Ohm connectors and chassis parts like BNC-75 Ohm or F-type connectors and use 75 Ohm resistors.
I was planning to use the Lemo Camac sytem with the 50 Ohm cables Mark Levinson was using in the eighties. It are nice thin cables that be easily bundled to one, and I have a large bunch of them. Still waiting for the parts!
[Lemo series 00 (NIM-CAMAC) can be used with RG58C/U, RG174 A/U, RG178 B/U. I guess the Levinson cable is the RG174.]
The signals WS, BCLK and DATA are best taken off at the digital output IC PCF2705P at the component side of the PCB. For the latter:
Pin 1 = WS
Pin 2 = BCLK
Pin 3 = DATA.
Hi Andrea,
Great you got these players!
Of course 75 Ohm coax cables can also be used. In this case use 75 Ohm connectors and chassis parts like BNC-75 Ohm or F-type connectors and use 75 Ohm resistors.
I was planning to use the Lemo Camac sytem with the 50 Ohm cables Mark Levinson was using in the eighties. It are nice thin cables that be easily bundled to one, and I have a large bunch of them. Still waiting for the parts!
[Lemo series 00 (NIM-CAMAC) can be used with RG58C/U, RG174 A/U, RG178 B/U. I guess the Levinson cable is the RG174.]
The signals WS, BCLK and DATA are best taken off at the digital output IC PCF2705P at the component side of the PCB. For the latter:
Pin 1 = WS
Pin 2 = BCLK
Pin 3 = DATA.
I hope to receive them soon and to play a little with them.
I think I'll try a external non-os DAC first and then wire a TDA1543 (and also a 1541A) with IIS..
If I want to make the DAC internal do you suggest direct connection (maybe with a separate supplt for the TDA) or a interface like the one you attached?
Can the Asynchronous reclocker (PS can you send me the schematic, please ) be useful in case I take out the IIS signal directly ?
Cheers
Andrea
I think I'll try a external non-os DAC first and then wire a TDA1543 (and also a 1541A) with IIS..
If I want to make the DAC internal do you suggest direct connection (maybe with a separate supplt for the TDA) or a interface like the one you attached?
Can the Asynchronous reclocker (PS can you send me the schematic, please
) be useful in case I take out the IIS signal directly ? Cheers
Andrea
ASR
Hi Andrea,
The Asynchronous Reclocker can be used between the connnectors J2, J5 and J6 and the TDA1543.
If this is usefull I doubt as there is no PLL and SPDIF interface causing jitter. Anyway I am not using the ASR with I2S direct.
Schematic is on the mail.
Andypairo said:I hope to receive them soon and to play a little with them.
I think I'll try a external non-os DAC first and then wire a TDA1543 (and also a 1541A) with IIS..
If I want to make the DAC internal do you suggest direct connection (maybe with a separate supplt for the TDA) or a interface like the one you attached?
Can the Asynchronous reclocker (PS can you send me the schematic, please
Cheers
Andrea
Hi Andrea,
The Asynchronous Reclocker can be used between the connnectors J2, J5 and J6 and the TDA1543.
If this is usefull I doubt as there is no PLL and SPDIF interface causing jitter. Anyway I am not using the ASR with I2S direct.
Schematic is on the mail.
CD931 Mods
Hi Andrea,
Well I almost did not do anything to mod this player. I only installed the KWAK-CLOCK-6. Later replaced the powersupply diodes by ultrasoft recovery MSR860 but in this model it brought almost nothing. And I changed the grounding. Separate ground for case to safety ground. Just plastic washers under the screws holding the PCB and disconnected ground for headphone amp.
Ciao
Hi Andrea,
Well I almost did not do anything to mod this player. I only installed the KWAK-CLOCK-6. Later replaced the powersupply diodes by ultrasoft recovery MSR860 but in this model it brought almost nothing. And I changed the grounding. Separate ground for case to safety ground. Just plastic washers under the screws holding the PCB and disconnected ground for headphone amp.
Ciao
Re: ASR question
Hi Andrea,
The second flip-flop is to counteract the metastability problem with a asynchronous clock.
With my AD1865 DAC my neighbor heard very faint dropouts I did not even notice. My neighbour seems to have very acute hearing as he can hear his nephew coming from 1 km. This of course lead to making me the remark if his nephew also made these bleeps.
It turned out to be the sound of his motorcycle.....
There are a lot of articles on the web about the metastabilty with excellent explanations so I will not give any links. If you put the word metastability in Google you will find enough to read for hours.
In concluding I can say that the second flip-flop cures the problem. The dropouts could be seen on the scope with a 3150 Hz tone on a testdisc. Interestingly the TDA1543 is less sensitive to metastability.
Andypairo said:
Hi Andrea,
The second flip-flop is to counteract the metastability problem with a asynchronous clock.
With my AD1865 DAC my neighbor heard very faint dropouts I did not even notice. My neighbour seems to have very acute hearing as he can hear his nephew coming from 1 km. This of course lead to making me the remark if his nephew also made these bleeps.
It turned out to be the sound of his motorcycle.....There are a lot of articles on the web about the metastabilty with excellent explanations so I will not give any links. If you put the word metastability in Google you will find enough to read for hours.
In concluding I can say that the second flip-flop cures the problem. The dropouts could be seen on the scope with a 3150 Hz tone on a testdisc. Interestingly the TDA1543 is less sensitive to metastability.
async reclocking question
Elso, I have a question about reclocking using your flip flop approach. Assuming that the incoming clock rates are going to be different from the master clock that does the reclocking, wont you start skipping samples as the delta timing between the clocks moves across the sample time domain?
Wouldn't a multibyte FIFO buffer with an adjustable master clock sync'd to the buffer almost empty/full flags be needed to avoid dropping samples? The flip flops you use are effectively a 1 bit FIFO buffer. I'm not talking about flipflop metastability, I can see how adding a second flipflop will help resolve this, I mean the fact that you get into a metastable state because of the async nature of the recovered clock & the master clock means that you loose the integrity of that particular sample not just the bit, and this will continue to recur many times a second as the two clocks continue to be out sync. If the above is not clear I will draw some diagrams.
I'm not meaning to be critical here, just trying to understand better how your mechanism works. As it is used by a number of people I'm sure it has good results and I will probably use it for my implementation.
Regards,
Dean
Elso, I have a question about reclocking using your flip flop approach. Assuming that the incoming clock rates are going to be different from the master clock that does the reclocking, wont you start skipping samples as the delta timing between the clocks moves across the sample time domain?
Wouldn't a multibyte FIFO buffer with an adjustable master clock sync'd to the buffer almost empty/full flags be needed to avoid dropping samples? The flip flops you use are effectively a 1 bit FIFO buffer. I'm not talking about flipflop metastability, I can see how adding a second flipflop will help resolve this, I mean the fact that you get into a metastable state because of the async nature of the recovered clock & the master clock means that you loose the integrity of that particular sample not just the bit, and this will continue to recur many times a second as the two clocks continue to be out sync. If the above is not clear I will draw some diagrams.
I'm not meaning to be critical here, just trying to understand better how your mechanism works. As it is used by a number of people I'm sure it has good results and I will probably use it for my implementation.
Regards,
Dean
Re: async reclocking question
Hi Dean,
To be quite honest I don't understand it either.
After bringing a synchronous clock from the transport to the DAC I was thinking let's do a silly experimemt: what will happen if I use a standalone asynchronous clock?. Later found out Kusunoki is doing exactly that with a 50 MHz clock and a 74AC74. He reclocks the WS and the BCLK but not the DATA. I found this approach, i.e. not reclocking the DATA, gave rise to a large lack of definition to the sound. And 74VHC logic sounds better than 74AC.
Thanks to my neighbour with his acute hearing I added the second flip-flop after studying a lot of articles about the metastability problem. I just guessed the beeps or dropouts were due to metastabilty.
I have a testdisc with a 3150 Hz tone that lasts ten minutes and during this time I don't see or hear any dropouts. So I guess two flip-flops are good enough. But there exists more elaborate schemes. I wanted to keep it as simple as possible, especially as there is no difference in sound between one or two flip-flops except the VERY faint bleeps I can only hear with the greatest concentration.
An other issue is the frequency of the reclocking clock. I found a higher frequency sounds better so I ended at about 66 MHz, with a 100 MHz crystal though. I will test the Vite 125 MHz oscillator. I need to make a PCB as this thingy is SMD and needs 3.3V supply.
As a tentative explanation I can offer that the jitter after the ASR is not data-related or has a different jitter spectrum. You can hear the clock in the ASR in your endresult: the sound. I tried a lot of clocks and crystals, also on 100MHz. The one in the schematic gave the best result.
I doubt if the ASR is beneficial with I2S Direct. Will do the experiment with the Vite oscillator nevertheless.
Don't get carried away, I prefer to omit the SPDIF interface alltogether.
deandob said:
Hi Dean,
To be quite honest I don't understand it either.
After bringing a synchronous clock from the transport to the DAC I was thinking let's do a silly experimemt: what will happen if I use a standalone asynchronous clock?. Later found out Kusunoki is doing exactly that with a 50 MHz clock and a 74AC74. He reclocks the WS and the BCLK but not the DATA. I found this approach, i.e. not reclocking the DATA, gave rise to a large lack of definition to the sound. And 74VHC logic sounds better than 74AC.
Thanks to my neighbour with his acute hearing I added the second flip-flop after studying a lot of articles about the metastability problem. I just guessed the beeps or dropouts were due to metastabilty.
I have a testdisc with a 3150 Hz tone that lasts ten minutes and during this time I don't see or hear any dropouts. So I guess two flip-flops are good enough. But there exists more elaborate schemes. I wanted to keep it as simple as possible, especially as there is no difference in sound between one or two flip-flops except the VERY faint bleeps I can only hear with the greatest concentration.
An other issue is the frequency of the reclocking clock. I found a higher frequency sounds better so I ended at about 66 MHz, with a 100 MHz crystal though. I will test the Vite 125 MHz oscillator. I need to make a PCB as this thingy is SMD and needs 3.3V supply.
As a tentative explanation I can offer that the jitter after the ASR is not data-related or has a different jitter spectrum. You can hear the clock in the ASR in your endresult: the sound. I tried a lot of clocks and crystals, also on 100MHz. The one in the schematic gave the best result.
I doubt if the ASR is beneficial with I2S Direct. Will do the experiment with the Vite oscillator nevertheless.
Don't get carried away, I prefer to omit the SPDIF interface alltogether.
Hi Elso,
I think what is happening here is that your method creates a stable low jitter clock after the flip flops with regular samples (words) dropping out as the delta between the clocks rotates across the word time boundries. However just dropping or corrupting one word in a contiguous stream of correct words is will sometimes be inaudible, even if these words are corrupted on a regular basis (several times a second).
I did some testing using the wav editor in Exact Audio Copy. I selected a sample of music and adjusted a single sample significantly higher or lower than the actual. Depending on the music it was detectable as a very slight click, and if I 'corrupted' samples on a regular basis (every 50 ms or so) it became quite apparent as a 'zzz' sound.
So your scheme must either only corrupt the odd sample or the delta between the real & the corrupted value is only small so the corrupted sample blends in with the samples before and after.
This is probably worthy of extra study. Have you checked the output of your DAC using a CRO or record the output through a soundcard for analysis? I'd be interested to see what happens. A first principles study on the clock timing of the circuit may also highlight what is going on.
Interesting.
Regards,
Dean
I think what is happening here is that your method creates a stable low jitter clock after the flip flops with regular samples (words) dropping out as the delta between the clocks rotates across the word time boundries. However just dropping or corrupting one word in a contiguous stream of correct words is will sometimes be inaudible, even if these words are corrupted on a regular basis (several times a second).
I did some testing using the wav editor in Exact Audio Copy. I selected a sample of music and adjusted a single sample significantly higher or lower than the actual. Depending on the music it was detectable as a very slight click, and if I 'corrupted' samples on a regular basis (every 50 ms or so) it became quite apparent as a 'zzz' sound.
So your scheme must either only corrupt the odd sample or the delta between the real & the corrupted value is only small so the corrupted sample blends in with the samples before and after.
This is probably worthy of extra study. Have you checked the output of your DAC using a CRO or record the output through a soundcard for analysis? I'd be interested to see what happens. A first principles study on the clock timing of the circuit may also highlight what is going on.
Interesting.
Regards,
Dean
Get rid of SPDIF
I've been looking into how to minimise jitter and have come to the conclusion like you that its better to get rid of the SPDIF circuit and use I2S directly. I want to connect a high quality DAC to a computer soundcard and am thinking the best bet is to use an external soundcard, replace its clock with a better one and share the clock between the soundcard & the DAC using the I2S interface between the two.
I've been looking into how to minimise jitter and have come to the conclusion like you that its better to get rid of the SPDIF circuit and use I2S directly. I want to connect a high quality DAC to a computer soundcard and am thinking the best bet is to use an external soundcard, replace its clock with a better one and share the clock between the soundcard & the DAC using the I2S interface between the two.
Re: Re: Re: I2S Direct
Hi Stefanobilliani,
No, no, no...... I meant powersupply bypass caps. 0.1µF from the +5V supply line to ground as close as posible at the logic IC and the transistors.
The whole scheme is direct coupled.
stefanobilliani said:
Hi ELSO,
The capacitors are "between" the SAA7310 and the logic IC and,
"between" the logic IC and the BJT ?
Hi Stefanobilliani,
No, no, no...... I meant powersupply bypass caps. 0.1µF from the +5V supply line to ground as close as posible at the logic IC and the transistors.
The whole scheme is direct coupled.
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