Thanks Mikeks for correcting me, But in that case the open loop gain would ultimately raise the Gate to Source voltage of mosfets to Turn-on and conduct heavy current through them, but if zeners were implemented , they would limit the gate to source voltage and hence output current is limited to a much safer value..meanwhile the protection circuit is engaged and input is muted so there would be no input signal . hence no output signal and amp is safe...
regards,
K a n w a r
regards,
K a n w a r
Workhorse said:
Indeed, with a dead short to ground, the foward-path gain of the voltage gain block preceeding the output stage will cause the former to saturate on its internal impedance....
Thus, the the TIS output node, (together with the MOSFET's gate), may saturate to within 10V of the supply rail, while the output (and the MOSFET's source), is firmly at zero volts...
Clearly then, a zener diode clamp (Vz=12V) is mandatory, to prevent gate oxide breakdown in the MOSFET, but does nothing to protect said MOSFET against high current-high voltage combinations at the output as may occur with a reactive load.....
....as, self-evidently, the zener diode is not in position to sense forbidden combinations of current and voltage through and across the MOSFET respectively...
mikeks said:
Hi Mikeks,
Yes the Zener has no effect when output is loaded with reactive loads, but if the output is resistive or a dead short..it could be made to limit the output current through each mosfet by implementing low Vz zener at gate to source terminals of mosfets....
Meanwhile, I have devised another circuit for short circuit protection.....and reactive discharge control
It senses both output Current as well as output voltage as key parameters , then the logic is applied to carry out the requisite decision...
If output voltage is Zero and current through Mosfet is High[enough high to prevent false triggring due to reactive loads], then the input signal to the amp is muted[input is shorted to ground]
If output voltage is high and current through mosfet is also high or above threshold of reference then no muting...amp is safe
If output voltage is low [tends to zero] and current is above reference threshold of permissible value [in accordance with SOA curve] then input signal is attenuated until it appears to be safe.....
correct me if i were wrong in any aspect....
regards,
K a n w a r
raveenvijendren said:
I've seen a couple of amplifiers with Bosch car relays in the output.
Even thought about using those myself before i saw them in commercial products, because of easy availibility, and got me one to see what there are like.
Contact resistance is high for an output relay, and response time is long, expect contact resistance to increase heavily over time.
On the other hand, in those years i've also seen a number of industrial type relays in familiar brand amplifiers.
I'd use a car relay if it's the only i could get.
janneman said:
Oh Janneman,
I have read that article one year ago, its just a VI limiter type in which all the operation is based around SHUNTING the BASE of driver transistor to the output in case of anything went wrong,
But look mine is a different approach, not tallying with Mikeks.....
He takes VCE and Ie of BJT and cooks the protection recipe...
I am taking Isource and Vout of Mosfet and devise another phenomenal circuitry...
K a n w a r
Kanwar,
Mikeks circuit is NOT a simple VI limiter, it is an SOA limiter. It is not "shunting the base current in case anything went wrong", it is precisely limiting the device power dissipation as a function of the SOA curve, to get the maximum output power from a given set of output devices. Are you sure you read it, and understood it?
SOA protection means you take account of the fact that the permissible device dissipation depends on the Vce or Vds. Lets say you have a 100W device. You may load it with 10A at Vce (or Vds) of 10V. But at Vce (or Vds) of 50V, you cannot load it with 2A, even if it is within the Pmax. So in any SOA protection circuit you need to introduce some non-linearity or breakpoints to model the SOA curve which you find in the data sheet.
Your circuit you call SOA limiter but from the description you give it is clear that it is a VI or power limiter. You do not model the SOA.
Jan Didden
Mikeks circuit is NOT a simple VI limiter, it is an SOA limiter. It is not "shunting the base current in case anything went wrong", it is precisely limiting the device power dissipation as a function of the SOA curve, to get the maximum output power from a given set of output devices. Are you sure you read it, and understood it?
SOA protection means you take account of the fact that the permissible device dissipation depends on the Vce or Vds. Lets say you have a 100W device. You may load it with 10A at Vce (or Vds) of 10V. But at Vce (or Vds) of 50V, you cannot load it with 2A, even if it is within the Pmax. So in any SOA protection circuit you need to introduce some non-linearity or breakpoints to model the SOA curve which you find in the data sheet.
Your circuit you call SOA limiter but from the description you give it is clear that it is a VI or power limiter. You do not model the SOA.
Jan Didden
janneman said:
Hi Jan,
I haven't said that Mikeks limiter was a "Simple" limiter, yes i know that its "SOA limiter", but the method used by Mikeks is another traditional type using a small-signal BJT for implementing limiting functions inaccordance with SOA parameters...devised to safe-guard the SOA of output trannies....
The SOA modelling of BJT is quite different from the Mosfets, because the BJT suffers from Second Breakdown Voltage, and if this condition is reached in BJT's there would be an instant failure of device results, but the case is very much different with mosfets, operation beyond their SOA curve for finite time doesnot let them to fail.......
Whereas my method uses something else....as it is designed for Mosfets only....
I just want to know that is there any CONDITION left from the previous posts , which would provoke device failure modes...
I really appreciate your comments on it....
regards,
K a n w a r
Workhorse said:
Well, then you must be clear that you talk about high voltage across ONE MOSFET and high current trough the OTHER MOSFET. But with complex loads the case is often that the high voltage and high current pertain to the SAME MOSFET. And that is precisely where you need a more sophisticated protection system. The amp is NOT safe then.
Jan Didden
Hi Jannneman & Workhorse,
you're having such a good discussion/argument it seems a shame to butt in.
The VI limiter whether single slope or multi slope can be applied to both BJTs and FETs.
The VI limiter can be a feedback system as Janneman is suggesting or the computed system by Workhorse. Both can stand a chance to work if correctly implemented. Both would also benefit if the limiting could take account of device temperature and so allow for the manufacturer's reduction in dissipation when Tc is above 25degC.
Both BJTs and FETs have a lower limit for DC conditions than for short term loading. My scant knowledge of the device parameters has led me to believe that a BJT gains more in short term loading than the FET, when short non repetitive peak currents are passed to the load.
The method of achieving the limiting should make no difference to the device protection and no difference to the audibility since all systems if working properly will protect the device under all conditions and will be inaudible when the device does not need that protection. In other words completely inaudible (no limiting) when the devices are within their dissipation limits (at any Tc and any current demand). This is completely different from the worst case senario e.g. Vrail diff *Ipk < Pmax at elevated C.
Best case senario:- both of you give us a working model to implement and a set of instructions on how to design it into our own amps.
you're having such a good discussion/argument it seems a shame to butt in.
The VI limiter whether single slope or multi slope can be applied to both BJTs and FETs.
The VI limiter can be a feedback system as Janneman is suggesting or the computed system by Workhorse. Both can stand a chance to work if correctly implemented. Both would also benefit if the limiting could take account of device temperature and so allow for the manufacturer's reduction in dissipation when Tc is above 25degC.
Both BJTs and FETs have a lower limit for DC conditions than for short term loading. My scant knowledge of the device parameters has led me to believe that a BJT gains more in short term loading than the FET, when short non repetitive peak currents are passed to the load.
The method of achieving the limiting should make no difference to the device protection and no difference to the audibility since all systems if working properly will protect the device under all conditions and will be inaudible when the device does not need that protection. In other words completely inaudible (no limiting) when the devices are within their dissipation limits (at any Tc and any current demand). This is completely different from the worst case senario e.g. Vrail diff *Ipk < Pmax at elevated C.
Best case senario:- both of you give us a working model to implement and a set of instructions on how to design it into our own amps.
AndrewT said:
Hi Andrew,
I agree on all accounts with you. Whatever the method of implementing, it is the concept that counts. And yes BJT's are more prone to secondary breakdown than power fets.
I pointed to Mikeks paper because it is a very effective and low cost solution (2 small signal transistors and a few passive elements). Brushing it off as "just a VI limiter" points to a fundamental misunderstanding of the concept described in the article series.
And sure, anybody can come up with his own implementation of whatever he fancies. If Kanwar thinks he prefers input muting, with the attendant problems of setting attack and sustain times, audible clicks and pops, over output limiting which would be unaudible in all but the most persistent overloads, its his money.
If he wants to spend a whole box of components rather than the two bjt's and a couple of resistors, by all means.
I just wanted to note that there's more involved in this kind of safety stuff than meets the eye.
I did implement Mikeks system in my amp. I added one more break point so I can have Icmax at any voltage below 10Vce, although as Mikeks told me, the practical use of it is probably very low. And no, I am not going to give you a set of instructions etc. Its all there in Mikeks article. At this point in time I see no possibility to improve on it, with the possible exception to adding some time relationship, to model the SOA for less than 100% duty cycle loads.
Jan Didden
using an analog computer circuit to compute the Pc of the output devices real-time, modelled to the SOA including the duration of the dissipation. But it DID work pretty good!
Hi Jan,
They did the same analog modeling of the output junction temperature in the Counterpoint SA-220. Every one was jumpered to the least sensitive position from the factory. Used an entire pcb for each channel and sensed the heatsink temperature too, and didn't use it.
Didn't stop them from going bang either.
-Chris
They did the same analog modeling of the output junction temperature in the Counterpoint SA-220. Every one was jumpered to the least sensitive position from the factory. Used an entire pcb for each channel and sensed the heatsink temperature too, and didn't use it.
Didn't stop them from going bang either.
-Chris
Hi Janneman,
I see two possibilities for improving the IV limiting;- temperature compensation and time compensation. Both of these are referred to in your reply or in the subsequent postings.
Time comp could simply be a cap from Prot Tr base to output. But something a little more sophistcated may be required than what is often seen in schematics. Temp comp will need to be a bit more than locating Prot Tr on the output heatsink but this does give a part compensation.
Continue your conversation with Workhorse & we will follow the outcomes.
Your observation that BJTs suffer secondary breakdown is not in dispute. Workhorse stated his position somewhat more emphatically and in my view substantially incorrectly. The short term capability of FETs is no better than BJTs and may be worse, not as Workhorse stated
I see two possibilities for improving the IV limiting;- temperature compensation and time compensation. Both of these are referred to in your reply or in the subsequent postings.
Time comp could simply be a cap from Prot Tr base to output. But something a little more sophistcated may be required than what is often seen in schematics. Temp comp will need to be a bit more than locating Prot Tr on the output heatsink but this does give a part compensation.
Continue your conversation with Workhorse & we will follow the outcomes.
Your observation that BJTs suffer secondary breakdown is not in dispute. Workhorse stated his position somewhat more emphatically and in my view substantially incorrectly. The short term capability of FETs is no better than BJTs and may be worse, not as Workhorse stated
Both FETs and BJTs fail if taken outside their respective SOAR whether DC or short term. The question might be how much outside and for how long or how often. Protection that includes a short term memory of the recent dissipation history might be able to account for this, but are we into computed protection for this?
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