Non-feedback parametric linearisation in FETs

[Cortez]

And nothing drawback ?
If there are only benefits, this could be produce in a single
case, like a normal FET with the 3 pins, couldnt ?.

 

[x-pro]

And nothing drawback ?
If there are only benefits, this could be produce in a single
case, like a normal FET with the 3 pins, couldnt ?.

Nothing is perfect . Thermal drift of characteristics is one of the problems (not unsurmountable thought ) . It is possible to produce a "3-pin device" using this approach, however I am not sure that this would be economical.

Alex

 

[LineSource]

HI X-Pro,

I designed and constructed several amplifiers with JFET cascode differential input stages on a +/- 12V supply and learned:

1) the wide variation in JFET transconductance and Vt can easily swamp out any linearization provided by a cascode differential topology if the JFETs were not carefully parameter screened and matched.
2) a low input impedance, like 100 ohms, takes away most of the advantages of the cascode’s reduced input capacitance.
3) the cascode differential has a lower F3 than a standard diff
4) cascode linearization is less effective at low power supply voltages
5) the more transistors, the more noise


Any other experiences with JFET differential cascodes?

 

[x-pro]

Hi LineSource,

As I was looking only at SE stage, and you are talking about differential, it is only partially relevant.

HI X-Pro,

I designed and constructed several amplifiers with JFET cascode differential input stages on a +/- 12V supply and learned:

1) the wide variation in JFET transconductance and Vt can easily swamp out any linearization provided by a cascode differential topology if the JFETs were not carefully parameter screened and matched.

That is always a problem using JFETs - in most circuits. However linearisation in my circuit does not work in the same way as linearisation in a differential stage so it presents a set of different problems. Careful pair matching is required however for two channel audio where same parameters of both channels needed.

2) a low input impedance, like 100 ohms, takes away most of
the advantages of the cascode’s reduced input capacitance.

Here I am at a loss - a FET cascode has HIGH input impedance on the gate of the "lower" transistor. Same would be true for a cascoded differential FET stage.

3) the cascode differential has a lower F3 than a standard diff

OK

4) cascode linearization is less effective at low power supply voltages

Yes, thought what is a "low voltage" would depend on particular transistors used.

5) the more transistors, the more noise

Yes, however the noise contribution of each transistor would depend on topology. A differential stage would have at least 3 dB more noise as two transistors would have an equal contribution, but for an SE cascode as in my circuit, the contribution of the top device is substantially less because in this circuit it has lower noise gain.

Any other experiences with JFET differential cascodes?

I had build differential cascodes in the past, however the purpose of this particular circuit was to provide high linearity in a single- ended, not in a differential configuration. You can apply the same idea for two sided of a differential pair, thought it would require a very careful matching and would not be as beneficial as in a SE stage.

Alex

 

[Ultima Thule]

Hi Alex,

thanks for your answers!
Now I have some more questions.

I am not sure with the abbreviation "knee", I guess it's some working point for the JFET.
Is it at the Vds point for a given Vgs where the Id doesn't rise anymore?

I attach a picture trying to illustrate my question:

edit:

Picture attaching don't seem to work, I try to put just the link here: "knee"


About your JFET cascode parametric linearising circuit, you say on your homepage that the lower FET drain voltage should be under the knee, is this the so called "linear" region and compared to tubes the area where the FET works as an penthode/triode or..?

But if I understand right the upper FET should then work "above" the knee or is it somewhere at the knee?

Comments from others are also wellcome!

Michael

 

[x-pro]

Hi Michael!

Hi Alex,

thanks for your answers!
Now I have some more questions.

I am not sure with the abbreviation "knee", I guess it's some working point for the JFET.
Is it at the Vds point for a given Vgs where the Id doesn't rise anymore?

I attach a picture trying to illustrate my question:

edit:

Picture attaching don't seem to work, I try to put just the link here: "knee"

Your picture is correct. "Lower" FET in my circuit works below this "knee", in the "linear" region.

About your JFET cascode parametric linearising circuit, you say on your homepage that the lower FET drain voltage should be under the knee, is this the so called "linear" region and compared to tubes the area where the FET works as an penthode/triode or..?

But if I understand right the upper FET should then work "above" the knee or is it somewhere at the knee?

Comments from others are also wellcome!

Michael

The "upper" FET works in a "normal" way with the drain voltage well above the knee but it has to provide the right working point for the "lower" device, where it's transfer characteristic will be linearised.

Cheers

Alex

 

[Ultima Thule]

Alex,

I wonder is it possible to put another cascode transistor(a third transistor) on top of the circuit discussed so it can work with even higher voltage than Max Vds allowed for the upper FET?

Or is the upper FET working condition sensitive/dependent on the drain resistor/load so it works as thought to provide the lower FET the optimal working condition?

Michael

 

[x-pro]

Originally posted by Ultima Thule Alex,

I wonder is it possible to put another cascode transistor(a third transistor) on top of the circuit discussed so it can work with even higher voltage than Max Vds allowed for the upper FET?

Or is the upper FET working condition sensitive/dependent on the drain resistor/load so it works as thought to provide the lower FET the optimal working condition?

Michael

Michael, it would depend on a particular transistor type, however it certanly makes sense if you want very high gain and/or voltage.

Also I would like to add another link to my article, as my site at the moment is not accessible .

Here it is:

http://vlab.netsys.ru/downloads/Parametric_Linearisation.pdf

Cheers

Alex

 

[ergo]

Hi Alex,

Nice idea, though I know it from before already.

One of my friends is using the FET's in the same way. But there is one more point there. You can actually go beyond 0V to reverse bias the fet upto 0.6V. This way the same linear region of the curve can be exploited even better.....

Ergo

 

[x-pro]

Hi Alex,

Nice idea, though I know it from before already.

One of my friends is using the FET's in the same way. But there is one more point there. You can actually go beyond 0V to reverse bias the fet upto 0.6V. This way the same linear region of the curve can be exploited even better.....

Ergo

Hi Ergo,

Does he also use the "lower" FET in a linear region? Or it is just a cascode? Obviously you can bias the FET in several different ways - the schematics illustrate only the simplest one of these . The essence of the idea is to use the "lower" transistor below the "knee" in the linear region. The rest is engineering .

Alex

 

[Ultima Thule]

Michael, it would depend on a particular transistor type, however it certanly makes sense if you want very high gain and/or voltage.

Alex,

I'm not following you here, when saying depending on particular transistor type do you mean the third cascoding transistor I was wondering about?

And second you say it make sense if we want very high gain/or voltage, maybe my question was misunderstood, my focus was not on high gain/signal voltage rather the second cascode transistor was added so the citcuit could be fed with high voltage like 70V for instance which will normaly break a JFET.
What i try to ask is if the upper JFET cascode transistor still work as suposed even if the drain voltage is kept firm with a second cascode transistor because with a drain resistor the drain voltage is changing with input signal.

I attach a picture (if this work).

Michael

 

[x-pro]

Alex,

I'm not following you here, when saying depending on particular transistor type do you mean the third cascoding transistor I was wondering about?

And second you say it make sense if we want very high gain/or voltage, maybe my question was misunderstood, my focus was not on high gain/signal voltage rather the second cascode transistor was added so the citcuit could be fed with high voltage like 70V for instance which will normaly break a JFET.
What i try to ask is if the upper JFET cascode transistor still work as suposed even if the drain voltage is kept firm with a second cascode transistor because with a drain resistor the drain voltage is changing with input signal.

Michael,

yes, this configuration will work very well and will only improve the linearity a bit further.

Cheers

Alex

 

[Elso Kwak]

Alex,
I'm not following you here, when saying depending on particular transistor type do you mean the third cascoding transistor I was wondering about?

And second you say it make sense if we want very high gain/or voltage, maybe my question was misunderstood, my focus was not on high gain/signal voltage rather the second cascode transistor was added so the citcuit could be fed with high voltage like 70V for instance which will normaly break a JFET.
What i try to ask is if the upper JFET cascode transistor still work as suposed even if the drain voltage is kept firm with a second cascode transistor because with a drain resistor the drain voltage is changing with input signal.

I attach a picture (if this work).



Michael

An example can be found here:
http://www.diyaudio.com/forums/showthread.php?postid=507432#post507432
and the configuration is also used by Erno Borbely.
http://www.borbelyaudio.com/home_theater.asp

 

[x-pro]

An example can be found here:
http://www.diyaudio.com/forums/showthread.php?postid=507432#post507432
and the configuration is also used by Erno Borbely.
http://www.borbelyaudio.com/home_theater.asp

This circuit itself is well known for ages and used by many people. I myself did use a similar circuit at least 20 years ago. However Ultima Thule was asking if this configuration is OK if you make use of the linearisation effect I wrote about. And the answer is - yes, it only would make the circuit even more linear.

Cheers

Alex

 

[Ultima Thule]

Thanks both Elso, Alex!

Alex, are you perhaps DC biasing the input signal in some way?

Cheers

 

[x-pro]

Thanks both Elso, Alex!

Alex, are you perhaps DC biasing the input signal in some way?

Cheers

No, I try not to use an input capacitor, so the input is connected direct (or with RC LPF) . You can bias the input negative till you reach the right point, however than you'll need to use a capacitor. Best results soundwise I've achieved by a careful selection of both JFETs in such a way that there is no need for the source resistor - i.e. the input connected to the gate of the "lower" FET and its source connected directly to the ground. This way there is no feedback whatsoever applied. However you'll need to limit the input voltage by about 1V p-p , so the gate is not conducting and there are not that many devices you can select - I get about 4 (enough for two channels) out of a hundred JFETs.

Alex

 

[Ultima Thule]

Ok, actually I felt from the verry first beginning that the lower JFET must be "bigger" than the upper device to achieve correct working point without manipulating the working point for each device without to add circuit complexity, but i might be wrong in my assumption.
But if we would manipulating the working condition for each device I think it must be possible to use the same device for both upper and lower, but this should be studied closer so I'm not sure of this idea, but again circuit complexity grows.

Michael

 

[Mike Gergen]

I did a similar circuit. The lower fet needed to have a lower pinch off voltage than the upper fet. Such as a 2SK170 with a 2SK246 as the cascode device. In some instances the same fet could be used for both but the biasing was critical.

I like this arrangement a lot.

 

[x-pro]

I did a similar circuit. The lower fet needed to have a lower pinch off voltage than the upper fet. Such as a 2SK170 with a 2SK246 as the cascode device. In some instances the same fet could be used for both but the biasing was critical.

I like this arrangement a lot.

What I did is in fact, exactly the opposite - I use the "upper" device with lower "pinch off" voltage than the "lower" FET. Read my paper here:

http://vlab.netsys.ru/downloads/Parametric_Linearisation.pdf

With a certain combination of these two FET parameters, where the "lower" FET works in the linear region, the transfer characteristic of this circuit could be 8-10 times more linear than for one FET or a normal cascode like you've described.

Alex

 

[Mike Gergen]

I stand corrected