1) Vis a Vis clocking - My current thought is to have the clock source as close to the DAC as possible. A pure, I am even thinking SAW stabilized clock source if I can get an appropriate frequency. That would run into a low jitter latch source. This would absolutely not be a PLL source, but a pure oscillator source. It would run slightly slower than the input source, with the DSP/Memory buffering. At the end of a song on the player, the memory would be read out until the song is over. Again, think cheap anti-skip on portable CD players. It is no more difficult.
- Okay, so we have one goal, perfect clocking. Yes there are other ways, but this is easy once set up.
2) The DSP will do the basic oversample.
- You know, an analog Bessel at this point may be just as easy as anything. However, digital higher order filters are easier to build and more reliable. It could end up being a minimum phase FIR filter as well.
3) Who knows, maybe a combination of a linear phase FIR and a mininum phase IIR will offer the best results? I would like to play with where the cutoff frequency is as well, to optimize in-band artifacts, analog filters, phase issues, etc. I need a flexible platform for this. However, I do not see this flexible platform as being overly difficult.
Give me some time, and I will throw together a block diagram.
Alvaius
- Okay, so we have one goal, perfect clocking. Yes there are other ways, but this is easy once set up.
2) The DSP will do the basic oversample.
- You know, an analog Bessel at this point may be just as easy as anything. However, digital higher order filters are easier to build and more reliable. It could end up being a minimum phase FIR filter as well.
3) Who knows, maybe a combination of a linear phase FIR and a mininum phase IIR will offer the best results? I would like to play with where the cutoff frequency is as well, to optimize in-band artifacts, analog filters, phase issues, etc. I need a flexible platform for this. However, I do not see this flexible platform as being overly difficult.
Give me some time, and I will throw together a block diagram.
Alvaius
Regarding the oscillator you'll need to set it about 110ppm below ideal inc ase the source is 100ppm below ideal (assuming thats the worst you'll get) to ensure the memory doesn't empty.
Now lets say you have the source running at +100ppm (again assuming worst case scenario) that means the buffer will have to absorb 38.4 samples per second per channel for 192K input sample rate.
Now if you listen to a whole CD then thats 340992 samples for both channels. So in all that is a Megabyte of memory that you'll need. I don't know if that is doable but I just thought I'd throw some numbers around.
Doesn't the genesis digital lense have about half a Meg of memory.
Now lets say you have the source running at +100ppm (again assuming worst case scenario) that means the buffer will have to absorb 38.4 samples per second per channel for 192K input sample rate.
Now if you listen to a whole CD then thats 340992 samples for both channels. So in all that is a Megabyte of memory that you'll need. I don't know if that is doable but I just thought I'd throw some numbers around.
Doesn't the genesis digital lense have about half a Meg of memory.
Hello All,
I'd like to tell people about a new system I am working on. I don't want to threadjack, but this new system seems like it it will follow the same principle as this thread, ie having control over the digital filtering part of the D to A process, but I have a quite different method in place.
I am building a system where the main processing is done on a 2.26GHz Pentium 4 processor, and output to an external DAC via a high speed digital I/O card. The card is an adlink PCI7300A rev. B which outputs data at a rate of 20MHz, either 32 bits input or output, or 16bits input and 16bits output. Currently I own the P4 and the Adlink card, and am in the process of designing the DAC.
The other major part of the system is the crossovers which is done in the digital domain, and output via the adlink card to an 8 channel DAC, to go to 8 amplifiers and then a 4 way stereo loudspeaker. The DAC is my major concentration at the moment, and will comprose the following:
Sub-bass and mid-bass will be output via a Burr-Brown DSD1608, 8 channel DAC. 4 pairs of outputs will make up a balanced output. The data rate will be quite low, to lower computation requirements, probalaby 26.041kHz (20MHz / 768)
A single AD1853 to produce 2 balanced signals, it has a built in digital filter, selectable between 2, 4 and 8X. I chose this simply because I got some free on sample request and they have very good distortion and dynamic range figures, although I still have doubts about the delta-sigma DAC. I still have a lot of controll over the digital filtering I choose to implement.
4x PCM1704-k will produce 2 more balanced signals. The data input to these will either be direct from the Adlink card, or via the Burr-brown digital filter DF1706 will be able to be switched in to allow up to 8x digital filtering. I chose to allow this in case the P4 or the Adlink card imposes restrictions in the processing or data-output bandwidth.
The PCM1704 and AD1853 DAC's may be used for either the midrage or treble, depending on listening tests. A small PIC uP will be used to control the three main DAC chips, depending on input from the P4 processor.
All this will hopefully allow me to implement almost any filter I choose. The software for the P4 is underway, relying heavily on Intels C++ compiler and their related performance libraries.
I'd love to hear feedback on this approach, The P4 is not by any means as efficient as a dedicated DSD chip, but the resulting flexibility I'm ending up with is as good as it could possibly get I believe, I will be easily able to implement minimum phase, FIR, IIR or even non-OS filters.
Cheers, Adrian
I'd like to tell people about a new system I am working on. I don't want to threadjack, but this new system seems like it it will follow the same principle as this thread, ie having control over the digital filtering part of the D to A process, but I have a quite different method in place.
I am building a system where the main processing is done on a 2.26GHz Pentium 4 processor, and output to an external DAC via a high speed digital I/O card. The card is an adlink PCI7300A rev. B which outputs data at a rate of 20MHz, either 32 bits input or output, or 16bits input and 16bits output. Currently I own the P4 and the Adlink card, and am in the process of designing the DAC.
The other major part of the system is the crossovers which is done in the digital domain, and output via the adlink card to an 8 channel DAC, to go to 8 amplifiers and then a 4 way stereo loudspeaker. The DAC is my major concentration at the moment, and will comprose the following:
Sub-bass and mid-bass will be output via a Burr-Brown DSD1608, 8 channel DAC. 4 pairs of outputs will make up a balanced output. The data rate will be quite low, to lower computation requirements, probalaby 26.041kHz (20MHz / 768)
A single AD1853 to produce 2 balanced signals, it has a built in digital filter, selectable between 2, 4 and 8X. I chose this simply because I got some free on sample request and they have very good distortion and dynamic range figures, although I still have doubts about the delta-sigma DAC. I still have a lot of controll over the digital filtering I choose to implement.
4x PCM1704-k will produce 2 more balanced signals. The data input to these will either be direct from the Adlink card, or via the Burr-brown digital filter DF1706 will be able to be switched in to allow up to 8x digital filtering. I chose to allow this in case the P4 or the Adlink card imposes restrictions in the processing or data-output bandwidth.
The PCM1704 and AD1853 DAC's may be used for either the midrage or treble, depending on listening tests. A small PIC uP will be used to control the three main DAC chips, depending on input from the P4 processor.
All this will hopefully allow me to implement almost any filter I choose. The software for the P4 is underway, relying heavily on Intels C++ compiler and their related performance libraries.
I'd love to hear feedback on this approach, The P4 is not by any means as efficient as a dedicated DSD chip, but the resulting flexibility I'm ending up with is as good as it could possibly get I believe, I will be easily able to implement minimum phase, FIR, IIR or even non-OS filters.
Cheers, Adrian
Only comment is that once you use a sigma-delta DAC, you are giving up some control over the digital filtering as they oversampling and filter internally.
I like the simplicity of using a PC for digital signal processing. That P4 probably has about 50 times (if not more processing power than the DSP I was going to use).
I would be concerned about the overall clocking of the system. What will you do to ensure minimal jitter on your DAC? For the system I propose, a crystal near the DAC will be the master for the system. The DSP clock will be generated off the DAC clock with a PLL.
The other concern I have with PCs, is that their switching power supplies tend to generate a lot of noise. I would watch for that getting into your DAC and jittering your clock.
Alvaius
I like the simplicity of using a PC for digital signal processing. That P4 probably has about 50 times (if not more processing power than the DSP I was going to use).
I would be concerned about the overall clocking of the system. What will you do to ensure minimal jitter on your DAC? For the system I propose, a crystal near the DAC will be the master for the system. The DSP clock will be generated off the DAC clock with a PLL.
The other concern I have with PCs, is that their switching power supplies tend to generate a lot of noise. I would watch for that getting into your DAC and jittering your clock.
Alvaius
Several people have mentioned running two clocks at different speeds to feed a RAM buffer. This is not necessary, since most syncronous FIFO's have a "half-full" flag , e.g.
http://www.cypress.com/cfuploads/support/app_notes/syncfifo.pdf
Also, if this is a standalone DAC then the data rate at the SPDIF input is set at 44.1 kHz. You guys don't want to build a transport too, do you?
http://www.cypress.com/cfuploads/support/app_notes/syncfifo.pdf
Also, if this is a standalone DAC then the data rate at the SPDIF input is set at 44.1 kHz. You guys don't want to build a transport too, do you?
The reason for running the output clock slower than the input is to guarentee that their is data in that FIFO. If I don't run it at a guarenteed slower rate, then I can not guarentee data in the FIFO and hence can't use this scheme. Remember that the output clock will not be PLL generated, but generated purely from a crystal and hence I can not tune it (well not easily at least) w.r.t. the input. I could go VCXO, but I want to keep it simple from an analog standpoint and as jitter free as simple. If I want to be a glutten for punishment, I may even consider doing a SAW stabilized oscillator, but that would likely mean custom frequency ordering and a cost beyond what I want, unless I hear a call for donations?? 
On the DSP, and I think someone already posted this, I am seriously considering the 6713 from TI due both to the performance and the available QFP package. I have access to ADI tools so I am somewhat motivated to stay in that direction. The ADI part is much better from an assembly language programming standpoint. TI's part can be programmed in C, but I know many that say the performance is absolutely no where near what TI says the C compiler can do and have ended up programming in assembler which is really messy with the C6X architecture.
I have a speaker project I need to finish first, but then I will be pursuing this... that or the class A amp... it never ends!
On the DSP, and I think someone already posted this, I am seriously considering the 6713 from TI due both to the performance and the available QFP package. I have access to ADI tools so I am somewhat motivated to stay in that direction. The ADI part is much better from an assembly language programming standpoint. TI's part can be programmed in C, but I know many that say the performance is absolutely no where near what TI says the C compiler can do and have ended up programming in assembler which is really messy with the C6X architecture.
I have a speaker project I need to finish first, but then I will be pursuing this... that or the class A amp... it never ends!
Hi Alvaius
You raise some good questions...
Only comment is that once you use a sigma-delta DAC, you are giving up some control over the digital filtering as they oversampling and filter internally.
You are right, and this is something I thought about for a while. As these were samples, I feel obliged to use them (and to save costs). I can choose either 2x, 4x or 8x oversampling, and apply my own filtering as well if I feel like it.
I like the simplicity of using a PC for digital signal processing. That P4 probably has about 50 times (if not more processing power than the DSP I was going to use).
The problem of the PC is it is not dedicated, and may run into problems if the OS (Win2K) decides to do other things. I don't feel like re-learning everything I know to change to a Low Latency Linux kernel. Tests with the Adlink card (has a 16k FIFO on the card) indicates it doesn't have problems with outputting 16bits at 20Mhz, but it can't do the full 32bits at 20MHz. This is just fine, as I only need around 9 output lines of data anyway.
I would be concerned about the overall clocking of the system. What will you do to ensure minimal jitter on your DAC? For the system I propose, a crystal near the DAC will be the master for the system. The DSP clock will be generated off the DAC clock with a PLL.
Clocking is something which I am thinking hard about. The only downside of the Adlink card is it is restricted to 10MHz when clocking data out, but can do 20MHz when using the internal crystal based timer. That is ample if I use the Digital filters to be built into the DAC, but not if I want to output 24bit data at around 800kHz direct to the PCM1704's. The card has a 40MHz crystal on board, and a 20MHz clock is output through a pin, so I should have a reasonibly precise clock to start with. I'm not sure if I should clean up the clock somehow on the DAC board, with a PLL, or just leave it alone and feed it staright to the DAC chips. Any thoughts anyone. I suppose I could remove the crystal from the Adlink card, put it into the DAC, and run a clock signal back to where the crystal came from.
The other concern I have with PCs, is that their switching power supplies tend to generate a lot of noise. I would watch for that getting into your DAC and jittering your clock.
I'm planning on having the PC located in a seperate room. As for digital noise entering the DAC through the data lines, I think good PCB layout with attention to track and ground impedances, and EFI, it will not be a problem. I discounted using ISO150's as they have very poor tolerances on their timing. As someone else in another thread said, "There is a good chance your data will arrive before your clock signal"
This project is still in it's early days, I'm fiddling around with producing software, and the DAC has just started being entered into Protel. I'll keep you posted on how it goes.
Cheers, Adrian
You raise some good questions...
Only comment is that once you use a sigma-delta DAC, you are giving up some control over the digital filtering as they oversampling and filter internally.
You are right, and this is something I thought about for a while. As these were samples, I feel obliged to use them (and to save costs). I can choose either 2x, 4x or 8x oversampling, and apply my own filtering as well if I feel like it.
I like the simplicity of using a PC for digital signal processing. That P4 probably has about 50 times (if not more processing power than the DSP I was going to use).
The problem of the PC is it is not dedicated, and may run into problems if the OS (Win2K) decides to do other things. I don't feel like re-learning everything I know to change to a Low Latency Linux kernel. Tests with the Adlink card (has a 16k FIFO on the card) indicates it doesn't have problems with outputting 16bits at 20Mhz, but it can't do the full 32bits at 20MHz. This is just fine, as I only need around 9 output lines of data anyway.
I would be concerned about the overall clocking of the system. What will you do to ensure minimal jitter on your DAC? For the system I propose, a crystal near the DAC will be the master for the system. The DSP clock will be generated off the DAC clock with a PLL.
Clocking is something which I am thinking hard about. The only downside of the Adlink card is it is restricted to 10MHz when clocking data out, but can do 20MHz when using the internal crystal based timer. That is ample if I use the Digital filters to be built into the DAC, but not if I want to output 24bit data at around 800kHz direct to the PCM1704's. The card has a 40MHz crystal on board, and a 20MHz clock is output through a pin, so I should have a reasonibly precise clock to start with. I'm not sure if I should clean up the clock somehow on the DAC board, with a PLL, or just leave it alone and feed it staright to the DAC chips. Any thoughts anyone. I suppose I could remove the crystal from the Adlink card, put it into the DAC, and run a clock signal back to where the crystal came from.
The other concern I have with PCs, is that their switching power supplies tend to generate a lot of noise. I would watch for that getting into your DAC and jittering your clock.
I'm planning on having the PC located in a seperate room. As for digital noise entering the DAC through the data lines, I think good PCB layout with attention to track and ground impedances, and EFI, it will not be a problem. I discounted using ISO150's as they have very poor tolerances on their timing. As someone else in another thread said, "There is a good chance your data will arrive before your clock signal"
This project is still in it's early days, I'm fiddling around with producing software, and the DAC has just started being entered into Protel. I'll keep you posted on how it goes.
Cheers, Adrian
alvaius:
I've come up with an alternate, and fairly simple solution to your clocking situation, and it doesn't involve any complex control loops, PLLs, or other convoluted circuitry. Here's how it works:
On the DAC end, you have a stable, low-jitter master oscillator clocking data out of your FIFO buffer, sending it to the DACs. Using a FIFO with "almost_full" and "almost_empty" flags allows you to do a binary decision on which of two clocks the transport is running from... one tuned a bit too slow, the other a bit too fast. Since jitter is irrelevant on this side, you can use simple Pierce oscillator circuits or whatever suits your taste, so long as it uses a discrete crystal and load capacitors, allowing you to tune the frequency roughly +/-200ppm. Selecting crystals made for either series or parallel mode operation can assist in the tuning. The low-jitter master oscillator will of course run at very close (probably +/- 50ppm or better) to the correct speed. There's a tiny bit of logic involved to make sure that the clock switch happens without any glitches or illegal timings for the transport, but it's possible to take care of this with just a few gates. Simply insert this dual-clock board in place of the transport's usual clock, and have one signal coming back from your FIFO to signal the switch.
What do you think?
I've come up with an alternate, and fairly simple solution to your clocking situation, and it doesn't involve any complex control loops, PLLs, or other convoluted circuitry. Here's how it works:
On the DAC end, you have a stable, low-jitter master oscillator clocking data out of your FIFO buffer, sending it to the DACs. Using a FIFO with "almost_full" and "almost_empty" flags allows you to do a binary decision on which of two clocks the transport is running from... one tuned a bit too slow, the other a bit too fast. Since jitter is irrelevant on this side, you can use simple Pierce oscillator circuits or whatever suits your taste, so long as it uses a discrete crystal and load capacitors, allowing you to tune the frequency roughly +/-200ppm. Selecting crystals made for either series or parallel mode operation can assist in the tuning. The low-jitter master oscillator will of course run at very close (probably +/- 50ppm or better) to the correct speed. There's a tiny bit of logic involved to make sure that the clock switch happens without any glitches or illegal timings for the transport, but it's possible to take care of this with just a few gates. Simply insert this dual-clock board in place of the transport's usual clock, and have one signal coming back from your FIFO to signal the switch.
What do you think?
hifiZen, all,
One other option is to use a standard (low jitter) oscillator and feed
the clock back to the transport. Use the 'empty' and 'half full' signals from
the Fifo to create a 'go' signal for clock/data to the DAC.
(connect to set and reset pin '74 FF).
I am working on this in combination with an old philips cd player.
Guido B
One other option is to use a standard (low jitter) oscillator and feed
the clock back to the transport. Use the 'empty' and 'half full' signals from
the Fifo to create a 'go' signal for clock/data to the DAC.
(connect to set and reset pin '74 FF).
I am working on this in combination with an old philips cd player.
Guido B
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