Ah but the context in which I said that was not multibit DACs (where I'm in total agreement with you) but low-bit ones. Low-bit DACs always are playing out some signal, even if totally inaudible.
I wasn't even on to considering the accuracy of the user's sample rate yet
But yeah, I think that's a non-issue.Sure, tiny. What is then "normal" for you? 8 bit audio will be good enough???
The jitter that influence the original accuracy of 16 bit is a bad jitter. "Tiny" or not...
The designer of the Anedio DAC has an interesting white paper on jitter on their website. James, the gentlemen mentioned, designed 20gb frequency dacs in the particle physics area. I think he knows what he is writing about. I suggest you read this paper. I am extremely pleased with his design, finding it a SOTA product. Regards
Do you mean this one:
Anedio Affordable High-End Audio : Multi-stage jitter reduction circuits that virtually eliminate jitter in the DAC output
If you do then I can certainly understand his stage 1 and 2. However stage 3 looks like its taken from ESS materials and its gobbledigook to me. Is there anyone here who can explain it?
Incidentally what's a "20gb frequency dac" when its at home?
Anedio Affordable High-End Audio : Multi-stage jitter reduction circuits that virtually eliminate jitter in the DAC output
If you do then I can certainly understand his stage 1 and 2. However stage 3 looks like its taken from ESS materials and its gobbledigook to me. Is there anyone here who can explain it?
Incidentally what's a "20gb frequency dac" when its at home?
I'm not so sure about stage 2 - does the local osc re-clocking the output not have to be synchronous to the incoming clock? Edit: Sorry, a PLL is used in stage 2 - but these always introduce jitter, no?
Stage 3 seems to me to be an explanation of how ASRC works, where intermediate sample have to be calculated, no? See here http://www.diyaudio.com/forums/digital-source/28814-asynchronous-sample-rate-conversion.html
Stage 3 seems to me to be an explanation of how ASRC works, where intermediate sample have to be calculated, no? See here http://www.diyaudio.com/forums/digital-source/28814-asynchronous-sample-rate-conversion.html
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The point being that the 'noise' associated with sample rate jitter scales with signal amplitude - I think. On low amplitude signals it is proportionately the same as at higher amplitudes in terms of amplitude relative to the output signal. If we reduce sample rate jitter so that it is inaudible on a full scale signal, it should remain inaudible at lower amplitudes, too. (This is different from quantisation error, where the effect becomes proportionately larger as signal amplitude decreases.) This suggests that even if we cannot reduce jitter to 1 LSB on a 24 bit full scale signal, we still get the benefit from higher bit depth at lower signal amplitudes. i.e. jitter doesn't negate the advantage of 24 bit over 16 bit, even if you can only reduce jitter noise to, say, 256 LSBs on a full scale 24 bit signal; when you're down below 16 bit amplitude the jitter noise isn't even 1 LSB of the 24 bit range. Maybe.
It sounds like total trash to me. 'Nearest neighbour' re-sampling of a sampled waveform combined with linear interpolation between sample transitions. You know it's total rubbish when he says
I'll bet you a fortune that that is just not true, and that people who know what they're doing can prove it, unlike this... person.
That's what I meant - I should have highlighted in bold.
(I was discussing sample rate converters yesterday in another thread, and I was making the point that yes, they change the samples but in a mathematically almost perfect way).
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I can't win!
If I were to put "perfect" someone would say "Of course it can't be perfect. That would be ridiculous".
If I put "almost perfect", someone leaps on it and says something profound like "An error is an error is an error"!
(No problem!)
Intuitively I think I realise that all these things are basically equivalent: PLLs, sample rate converters and so on - but not bodged D-type linear interpolator-splicer re-samplers!
The best system of all has to be for the DAC to be clocked by its own almost perfect clock, drawing on a FIFO, and to to have flow control feedback from the FIFO to the source. No PLLs, no re-sampling, jitter determined only by a single crystal super-oscillator.
The problems seem to start when we connect a source to a DAC without any flow control feedback. i.e. allowing the source to dictate the sample rate then sending it over a jitter-prone interface. I therefore pronounce most outboard DACs to be silly.
I just wondered how perfect this is if it is selecting the polyphase filter to apply to the incoming sample but doing so in a AVERAGE sense? I presume this works better than it at first might appear because the input clocks & output clocks don't change much. Maybe some experts can answer about the accuracy attained here?
As another piece to chew on - an Audiophileo is measured at 4pS jitter on it's output (I think) - yet when it's USB power is substituted with an external 5V supply, it is reported to improve the sound. Even though it's SPDIF output is said to be galvanically isolated? Anybody care to guess why the improvement with cleaner PS?
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As another piece to chew on - an Audiophileo is measured at 4pS jitter on it's output (I think) - yet when it's USB power is substituted with an external 5V supply, it is reported to improve the sound. Even though it's SPDIF output is said to be galvanically isolated? Anybody care to guess why the improvement with cleaner PS?
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Hi,
An alternative is to place the flow control in the DAC, but to make it very SLOW.
In practice, the FIFO and Clock in AMR's DAC will update once every few minutes with the smallest adjustment step (fractions of 1ppm of the clock) once the system has attained lock. So, a wide range of source clocks and even their wander can be adapted to, yet any source jitter is blocked.
Of course, given the limits of current common logic technology, it is not easy to make a DAC (any DAC)with jitter that is much lower than 100pS, no matter how good the clock.
Quite right too, quite right.
It is possible to do it differently.
I found the biggest issue is to achieve a sufficiently quick initial "lock" to prevent the FIFO from over/under-flowing...
Ciao T
An alternative is to place the flow control in the DAC, but to make it very SLOW.
In practice, the FIFO and Clock in AMR's DAC will update once every few minutes with the smallest adjustment step (fractions of 1ppm of the clock) once the system has attained lock. So, a wide range of source clocks and even their wander can be adapted to, yet any source jitter is blocked.
Of course, given the limits of current common logic technology, it is not easy to make a DAC (any DAC)with jitter that is much lower than 100pS, no matter how good the clock.
Quite right too, quite right.
It is possible to do it differently.
I found the biggest issue is to achieve a sufficiently quick initial "lock" to prevent the FIFO from over/under-flowing...
Ciao T
You may be interested in this link I posted earlier:
The D/A diaries: A personal memoir of engineering heartache and triumph
It describes the development of a PLL-based system which locks very quickly but then switches to a slowly adapting frequency correcting system.
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