Jitter in DAC.

[rfbrw]

ghee0,
Implementing the Mark Levinson 'Intelligent FIFO', especially the latest version which generates the clock to the dacs using Direct Digital Synthesis and involves working with QFP surface mount packages would be a case of extreme diy. The AD1896 route would be much simpler. The only thing I would add to the previous posts on the use of the AD1896 is that you might want to consider reclocking the clocks to the PCM1704 with d-type flip-flops clocked directly from the crystal.

ray.

 

[Petter]

If you make the DAC master clock the master, you don't need to reclock. What you do is use an ordinary input receiver in the ordinary way, but now you feed the MCLK (master clock) directly to the DAC chip. It is usually the MCLK which the DAC chip is most sensitive to.

Then you take the master clock, modify if necessary (for example divide by 2 if necessary) and use that to drive the sources component.

Unless you are very unlucky with timing, you now have an almost optimal solution. For a FIFO to work, you need to have an amount of buffer (time buffer) in it unless you have Master type control over all clocks.

If you check out http://www.lcaudio.com and http://www.lcaudio.dk there used to be an article on how to do what I have described above.

If you want, you can add a FIFO where the input receiver controls the input clocking, and the master clock controls the output. This can deadlock though ....

If you want, you can forgo the input receiver completely by transmitting L/Rclk, bitpattern etc. from source without first converting to serial S/PDIF.

Petter

 

[rfbrw]

Petter,
My suggestion has nothing to do with the source components.
The point of reclocking or pipelining between the digital filter and the dac is that it goes some way towards removing any jitter generated in the filter. Slaving the transport to the dac is a completely different issue.
ray.

 

[richt]

hi petter

thanks for your info!

my dac is the master clock 33.868megs & is divided by 2
for the servo dsp.
but i made a very simple reshape with 74hcoo just purpose of
tesing & ive found that i was loosing too much information
due to a jittery clock!!!
ok i am thinking to install the master clock from lcaudio
but if the servo dsp that feeds the dac again is jittery
poor inprovment will be heard!
i want to reclock too all the info that comes from the dsp!
i need info
thank you

 

[walk]

If you make the DAC master clock the master, you don't need to reclock. What you do is use an ordinary input receiver in the ordinary way, but now you feed the MCLK (master clock) directly to the DAC chip. It is usually the MCLK which the DAC chip is most sensitive to.

Then you take the master clock, modify if necessary (for example divide by 2 if necessary) and use that to drive the sources component.

Unless you are very unlucky with timing, you now have an almost optimal solution. For a FIFO to work, you need to have an amount of buffer (time buffer) in it unless you have Master type control over all clocks.

If you check out http://www.lcaudio.com and http://www.lcaudio.dk there used to be an article on how to do what I have described above.

If you want, you can add a FIFO where the input receiver controls the input clocking, and the master clock controls the output. This can deadlock though ....

If you want, you can forgo the input receiver completely by transmitting L/Rclk, bitpattern etc. from source without first converting to serial S/PDIF.

Petter

 

[walk]

Hi !

I have some questions .

Maybe not correct , but I call the LRCK , BCK and DATA as I2S here - much shorter anyway .
Can qulity of I2S from the receiver/decoder in separate DAC
be better then ´´ the same ´´from dsp in transport ?

I use Sony cdp xa 50 es as transport only and SDS Labs tubedac as separate dac . Now I take the I2S ( three connections + ground ) from sony dsp and feed it straight to NPC SM 5843 filter in the dac. 16 MHz masterclock signal is only thing I get from Sony audioboard . Hopefully next week will get new 16 MHz clock from LCAudio , and I put it in separate dac close SM 5843 . Here is my next question .
How feed the dsp with 16 MHz clocksignal ? Now I see two
ways , like example on LCAudio homepage ´´Separate dac´´
and secondly use SM 5843 buffered CKO (pin 9 ) oscillator output , clock same frequency as XTI .

Tõnu

 

[tiroth]

So, I would go with the ASRC approach. Right now I'm building several test DACs for my big DSP project (which keeps getting sidetracked). All of the test DACs use either AD1892 combination receiver/ASRC or the AD1896, which is a superb sample rate converter.

If one is using AD1896 ASRC, is there any benefit (from the standpoint of jitter) towards feeding the ASRC directly from the DSP's SDATA/SCK/LRCK versus feeding it from a S/PDIF reciever?

I think I am in a similar position; I am planning using a DSP to do some processing on an incoming biphase or serial stream, so I can build the DAC to accept either (or both). However, if there is no difference to overall jitter when it is being passed through the AD1896 I see no reason not to include S/PDIF inputs, since they will make the DAC compatible with more hardware.

If you ever get anywhere on this DSP project I would be very interested in hearing about it. I currently have a TI C6000 demo board which is probably not ideal for this purpose, so I'd be interested in the SHARC approach, provided software and hardware is available out there. ^_^

 

[tttking]

My DAC/Transport XCLOCK Experience

I have made the XCLOCK modification to my DAC/Transport with very good result. Please check out the whole report in 'clock upgrade for cd/dvd players' Section of this Digital Forum.

 

[hifiZen]

tiroth:

That's exactly what I'm planning to build. The AD1892 includes the SPDIF receiver, while the AD1896 allows for 24 bits, and higher sample rates. So, the 1896 would typically be coupled with a separate SPDIF reciever IC. The beauty of using an ASRC is that it changes all input data into a single sample rate for your DSP. Thus, your filter coefficients and DSP filter structures can remain the same regardless of the input data rate. This is a wonderful simplification which also allows you to choose a sample rate on the DSP side to maximize your processor useage for best quality.

I am planning to have my first DSP hardware platform running about 6 months from now. It will be based on the ADSP-21065L, for 8ch input, 8ch output at 24 bit, 48 or 96 kHz (DSP sample rate). 4x SPDIF receivers, 4x I2S outputs to separate DACs / SPDIF transmitters. The host micro will be the Atmel ATmega103 - plenty of GPIO. I'll post updates as I make progress.

 

[Petter]

All this is very interesting

Just for clarification:

A recovered clock is likely to be less perfect than a master clock.

A high quality master clock near DAC chip as master clock is usually considered to be the optimal approach. You can source such clocks from for example valpey fisher as I did. IF you go for the master scenario you only need a regular unit. I got lucky when I called them since they usually only sell in large custom lots. Very nice people. Then again, there are other high-end communication companies doing oscillators + LC audio etc.

Petter

 

[ftorres]

Correct me if I'm wrong...

Hi all,

Very interesting thread... I'd like to know your opinions, comments or flames on the following design proposal, which is not quite new, I must admit :

Imagine a low jitter master clock, either a commercial or a DIY one,

This clock feeds :

- A sample rate converter (CS8420 for example) for upsampling
- A digital filter
- A quad D flip-flop (clock input)
- and the D/A converters' Bit clock inputs (the BCK output of the digital filter is left NC)

The D inputs of the flip-flop are tied to the left and right data outputs and to the left/right clock outputs of the filter, and flip-flop's outputs drive the D/A converters' inputs.

Ouf course you may add some gates to delay or invert the clock (compensation of filter's propagation delay).

Is this kind of upsampling-reclocking of any interest regarding jitter reduction ? Any hints ?

P.S. : the complementary outputs of the flip-flop can be used to implement a balanced version of the DAC... (not a true 2's complement, but the error is quite negligible)

 

[hifiZen]

yep, that's how it's best done (IMHO). The D-ff timing is critical, so you must check the propogation delays and timing carefully. Fortunately, most DACs depend only on the bit clock or master clock for their jitter performance, and not the data and word clocks. So, depending on the DAC you use, the D-ff may not even be necessary. A good ASRC will nicely block the unwanted jitter coming in from the SPDIF line.

fyi: many DACs include a method for doing a proper signal inversion so you needn't worry about bit-flipping.

 

[hifiZen]

PS - a brief update: I will *finally* have a reliable, permanent server set up to host my webpage. So, hopefully in the next month or so, I'll be officially back online with the KA Audio website... and of course I'll be able to post updated information on the DSP. I'll post again when i get it all set up.

 

[ftorres]

Hi HifiZen,

Yes, the D-ff's timing is critical, but can be somewhat controlled using an IC containing all the FFs you need (74175 for example), the same process used on the chip minimizing the dispersions between the flip-flops (may be I'm too optmistic )

One of my biggest problem in such an implementation is the lack of informations concerning the digital filter I plan to use, namely a DF1704. I've sent e-mails to TI's technical support, but get only some "vapour" answers

I just wanted to know the propagation delays inside the chip, between the clock input and the outputs, just to know if I must invert or delay the clock input of the D-ffs. The datasheet just gives timing characteristics of the outputs with a 10 ns accuracy (+/- 5ns). The clock period being just 4 times larger , after some simulations, I decided to go with some "bypassable" Exor gates in the clock path to invert or delay the signal... The answer in a month or so, when I'm finished with the PCB...

Besides, happy new year to all

 

[Dave]

Small FIFO to solve timing problem.

ftorres,

Hi There,

I am also planning a project which will involve reclocking the data coming out of the oversampling filter (probably DF1704, DF1706) and have come up against the same issues as you have.

I have used the DF1704 in combinantion with the CS8420 and have found that with a clock frequency of 24.576 MHz an inverter works fine. However this may not be the case if the sampling rate (master clock frequency) is going to vary as the timing will change. I will not be using a SRC in my next DAC and thus this could be an issue.

I was thinking of placing a small FIFO (16 words by 4 bits) between the DAC chips and oversampling filter. These cost about a dollar fifty and would completely eliminate any timing problems. It would just be a matter of making sure that it doesn't get stuck in the full or empty condition. You would of course want minimal control logic.

What do you think?

 

[Dave]

The 74HC40105 is avaliable from digi-key and is a 16 word by 4 bit FIFO. It would be placed between the DF1704 and PCM1704 by loading the L/R and Word Clock through it. The bit clock of the DF1704 would clock the data into it and the low jitter master clock would load the data out of it and directly into the DACs. This should mean that the delay and timing through the over sampling filter would no longer be an issue.
Also unlike a D type flip-flop solution there are no setup and hold times to worry about.

The 74HC40105 has a empty and full flags and I am not quite sure how these should be used. They may not even be needed.

 

[ftorres]

Dave,

Sorry for the late answer, but I was on holidays 'till today, with no computer access...

The FIFO solution you propose seems to be fine. I'm not a FIFO specialist, and after a diagonal reading of the 40105 datasheet, it seems to be perfect for this application. I have to admit that up to now I have no idea of the way to use the full/empty flags

But as I intend to go with an ASRC, I'll go with the FFs (futhermore the PCB is almost finished )

IMHO, in both cases, the main point is to keep a perfect timing between the WordClock (which initiates the serial to // transfer inside te DAC) and the BitClock (which makes the DAC output change - 2 BCK periods after for the PCM1704). The timing correlation between the Data flow and the bitclock can be somewhat weaker. Pushing it to the limit, maybe the word clock could be directly derived from the master clock (/256), but the divider's output should be reclocked by the bit clock to account for its delay No way out !

By the way, keep us informed of your progresses with your design. Quite interesting !

 

[Dave]

Yes, the whole point is to synchronize the word clock and data with the locally generated master clock. I don't think it's possible to generate a new word clock with a divider because the word clock must correspond to the data bits as it tell the DACs when the samples start and stop in the stream of bits. I hope that makes sense!

I am planning to clock both the left and right data line and the word clock through the 40105.

I'm sure you'll be fine with the D ffs. I am going to investigate the 40105 further as the timing in my design will be very hard to setup with D ffs.

Basically the master clock (AD9850) is going to be generated on the analog PCB and be connected directly to the BCLK of the PCM1704s. It will also be isolated and sent back to the digital PCB. Here it will travel through some timing logic (for the large jitter removal FIFO), the oversampling filter and finally back to the analog PCB through another set of isolators.

I'll keep posting my progress.

 

[tiroth]

Basically the master clock (AD9850) is going to be generated on the analog PCB and be connected directly to the BCLK of the PCM1704s. It will also be isolated and sent back to the digital PCB. Here it will travel through some timing logic (for the large jitter removal FIFO), the oversampling filter and finally back to the analog PCB through another set of isolators.[/B]

Perhaps this is a naive response, but since the nominal jitter of the AD9850 output clock is 80ps and the nominal jitter of DIR-1703 is 75ps, with the added benefit of actually being a digital input reciever and FIFO buffer, what is the point of your more complex solution?

 

[Dave]

tiroth,

That's a good question and I think it is the result of a misleading specification from Texas Intruments. As far as I can tell the 75ps is the intrinisc jitter of the DIR1703 (Intrinisic jitter is defined as the output jitter with a jitter free input).
There does not appear to be anything on the datasheet to indicate the conditions to get 75ps - a bit suspect.

The more important characteristic is the jitter rejection of the
device and is in the case of the DIR1703 determined by the characteristics of the analog PLL used (again as far as I can tell from the datasheet). This is shown on page 7 of the datasheet and does not look to be very good at all.

The AD9850 solution is not like conventional PLL schemes. Instead the AD9850 generates a clock signal from a fixed oscillator reference. This is completely independent of the input clock and thus the jitter rejection is huge. To break the tight relationship between the output clock of the AD9850 and the recovered input clock a FIFO is employed. The output frequency of the AD9850 is adjusted very slightly every ten seconds or so to track the long term frequency variation of the input clock. This prevents the FIFO from filling or emptying.

The AD9850 is specified with 80ps jitter but this is using the internal comparator - I hope to achieve lower jitter than this with an external comparator. Whatever the figure though it still remains independent of the input clock to the DAC.

Here is a company the uses a FIFO based approach - www.dbtechno.com

Have a look at the DA924 DAC and the last page of the "on jitter" paper in the support section.

If anyone has anymore info on the DIR1703 I'd be most interested to hear about it.