Woow!
Big words. Let's see if mikelm can beat this.
What I miss,
besides the extra AKSA-resistor from input to ground (220k),
is a capacitor for the input bias.
You have 5k POT, I think.
From POT Wiper to ground. 10uF elyt-capacitor.
This will filter eventual noise or ripple from power supply rail.
And from the POT and LEDs.
We ca not give 'dirt' a chance to enter the sensitive input.
Otherwise, I take your words for a good circuit.
You have certaily learned a lot and quickly.
Thanks for being around my topic.
AKSA repeatedly has expressed your importance.
You are one glowing fire in this topic.
Regards
Hugh,
Voltage across R8 is 3.42v. No idea of OLG. Clipping was quite symmetrical as I recall.
Would love help with the PCB. I'll post a preliminary design over the coming days for y to look at.
I haven't done proper stability testing with capacitive loads yet, but the absolute absence of ringing on the 20kHz wave into a resistive load is very promising.
The vas current is a little high, but I thought it might help the rather agricultural 9610 sound a bit better. The bd139 might get a bit hot at these currents though. A small heatsink might be good.
I can't take any credit for this design, lineup posted pretty much the exact circuit in the first few posts of this thread. The only difference is your LED ccs and input bias, and my choice of a BJT CCS.
I thought I had put the fet vas and jfet to bed for good, even as recently as this afternoon, but the truth of the matter is they a made for each other. The jfet sounds terrible with the bjt vas and that's that. I was ready to write it off but it was nagging and nagging at me. Fortunately the bd140 and irf9610 have the same pinout so on a whim I swapped them and was very pleasantly surprised.
This weekend I have tried so many options, even a bjt input (which was quite good btw), but I have landed right back where we started.
Voltage across R8 is 3.42v. No idea of OLG. Clipping was quite symmetrical as I recall.
Would love help with the PCB. I'll post a preliminary design over the coming days for y to look at.
I haven't done proper stability testing with capacitive loads yet, but the absolute absence of ringing on the 20kHz wave into a resistive load is very promising.
The vas current is a little high, but I thought it might help the rather agricultural 9610 sound a bit better. The bd139 might get a bit hot at these currents though. A small heatsink might be good.
I can't take any credit for this design, lineup posted pretty much the exact circuit in the first few posts of this thread. The only difference is your LED ccs and input bias, and my choice of a BJT CCS.
I thought I had put the fet vas and jfet to bed for good, even as recently as this afternoon, but the truth of the matter is they a made for each other. The jfet sounds terrible with the bjt vas and that's that. I was ready to write it off but it was nagging and nagging at me. Fortunately the bd140 and irf9610 have the same pinout so on a whim I swapped them and was very pleasantly surprised.
This weekend I have tried so many options, even a bjt input (which was quite good btw), but I have landed right back where we started.
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I don't understand this.
My interpretation is that the output offset voltage (DC @ R17 & R18) is the same voltage as at the jFET, J1, source terminal, assuming there is zero leakage through the NFB DC blocker (C5).
If the jFET is run at Idss then Vgs = 0v and the Gate terminal will also be at the same output offset voltage.
If 9mA Idss jFET is run at a bias of 6mA then the J1 Vgs is ~ -100mV.
This is the voltage that the Gate is below the Source.
Set the output DC offset to 0mV and the Source voltage will also be at 0mV.
The jFET Gate voltage will be at ~-100mV cf. the speaker return voltage.
The other side of C1 is at input voltage. This is normally 0mVdc particularly so when the input is grounded with Rin ~50k to 220k.
If gate leakage is near zero then the bias voltage across C1 ~ 100mVdc
I cannot see how the C1 voltage can be around 2V.
If the input jFET J1 and C1 have a 2V bias applied to them , then the output offset will be ~2.1V
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Andrew,
R15 is 499R, and passes, apparently, about 4mA. This means it drops 2V. If the output offset is correctly set up to exactly 0V by the gate bias network, then clearly the source of the jfet will be at +2V. As you mention, the fb shunt cap should pass no current in this scenario.
Further, as you properly calculate, the gate would be around 50mV above this, at 2.05V.
That's the potential therefore on the RIGHT side of C1.
The LEFT side of C1, however, the input side, should be referenced to ground via a 220k resistor so as to mesh with the assumed zero output potential of any real world source.
Ergo the cap will have, in normal operation, some 2.05 volts of DC polarisation across it.
Hope this is clear!
Hugh
R15 is 499R, and passes, apparently, about 4mA. This means it drops 2V. If the output offset is correctly set up to exactly 0V by the gate bias network, then clearly the source of the jfet will be at +2V. As you mention, the fb shunt cap should pass no current in this scenario.
Further, as you properly calculate, the gate would be around 50mV above this, at 2.05V.
That's the potential therefore on the RIGHT side of C1.
The LEFT side of C1, however, the input side, should be referenced to ground via a 220k resistor so as to mesh with the assumed zero output potential of any real world source.
Ergo the cap will have, in normal operation, some 2.05 volts of DC polarisation across it.
Hope this is clear!
Hugh
SWF,
I think the stability is quite good, but, the ongoing, undamped overshoot concerns me.
First up, try about 47pF from drain of the VAS to the jfet source, and if that is not sufficient, add a 10pF silver mica miller cap across gate/drain of the VAS.
I hope this scotches the overshoot... and it should also improve the sound quality further.
Thanks, saw the 3.42V bias voltage; that presumably is around 1.7V Vgs for each output device.
Congratulations to Lineup for a great topology, thanks mate!
Cheers,
Hugh
I think the stability is quite good, but, the ongoing, undamped overshoot concerns me.
First up, try about 47pF from drain of the VAS to the jfet source, and if that is not sufficient, add a 10pF silver mica miller cap across gate/drain of the VAS.
I hope this scotches the overshoot... and it should also improve the sound quality further.
Thanks, saw the 3.42V bias voltage; that presumably is around 1.7V Vgs for each output device.
Congratulations to Lineup for a great topology, thanks mate!
Cheers,
Hugh
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Thanks Hugh, I will add those capacitors.
Here are some more measurements from the actual circuit for you (and you too AndrewT):
JFET gate bias voltage is actually 4.92V, quite high!
JFET Source voltage is 4.81V.
JFET Drain Voltage is 19.7V, therefore 14.89 volts across the JFET.
JFET drain resistor voltage drop is 4.8V, therefore input stage current is 9.6mA! a bit high!
Dissipation in JFET = 14.89 * 0.096 = 143mW....maybe pushing it a bit??
Here are some more measurements from the actual circuit for you (and you too AndrewT):
JFET gate bias voltage is actually 4.92V, quite high!
JFET Source voltage is 4.81V.
JFET Drain Voltage is 19.7V, therefore 14.89 volts across the JFET.
JFET drain resistor voltage drop is 4.8V, therefore input stage current is 9.6mA! a bit high!
Dissipation in JFET = 14.89 * 0.096 = 143mW....maybe pushing it a bit??
Actually the origin of the of this circuit was a development of lineups one rail circuit posted in this forum a long time ago...where I suggested to make it dual rail... I attached the circuit in post 10
http://www.diyaudio.com/forums/solid-state/172744-one-jfet-poweramp-looking-fet-sound.html
only difference is that I followed at path with a current mirror i ordet to control the current through the Jfet to gain a stable offset.
But the thread died...until it came alive here again.. thanks to lineup...
http://www.diyaudio.com/forums/solid-state/172744-one-jfet-poweramp-looking-fet-sound.html
only difference is that I followed at path with a current mirror i ordet to control the current through the Jfet to gain a stable offset.
But the thread died...until it came alive here again.. thanks to lineup...
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swordfishy, you are driving your JFET at positive Vgs (Id is higher than Idss).
Referred to the GND, your Source should have higher voltage then the Gate and Id has to be lower than Idss.
I think you mean IRF9610 (without 'P')
Actually I have 2 models of IRF9610.
First is from MultiSim11 ->Transistors->POWER_MOS_P
The second model called 'xirf9610' I found on the internet
I have no idea which is best. Can anybody tell?
But they do work both. I would probably go for the first. From MultiSim11
Hmm, yes you're right. Is this a serious problem? I had completely neglected to consider that. I will increase the drain resistor to 1k which should fix things. Fingers crossed this is not a significant contributor to the current sound of the amplifer!
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It is adviced to run at 70-80% of MAX IDSS
Now, JFETs are strange.
It is actually possible to over-drive!
But I would not do this.
And in this case there is no need for it.
The GATE of IRF9610 mosfet need only a couple of mA.
swordfishy
I would lower the JFET current to something like 70-80% of IDSS
For example 8mA IDSS I like to run ~5mA current = 62.5%
Now, JFETs are strange.
It is actually possible to over-drive!
But I would not do this.
And in this case there is no need for it.
The GATE of IRF9610 mosfet need only a couple of mA.
swordfishy
I would lower the JFET current to something like 70-80% of IDSS
For example 8mA IDSS I like to run ~5mA current = 62.5%
I see my mistake.
I forgot that there is no source resistor in this circuit.
All the Source current has to pass through the upper NFB resistor (R13 = 499r).
The jFET bias current passes from +ve supply through Drain resistor (R4 = 499r), through J1 through R13 and finally through the speaker to the speaker return terminal.
This leads to +ve voltages for all points in that string above the speaker return terminal.
Setting the speaker Return terminal to 0V, the speaker must have a +ve output offset when J1 passes bias current.
Each +ve voltage in that string can be found from I * R to ground.
Return terminal I * 0 = 0V0
Speaker feed Terminal = output offset = I * Res (speaker DC resistance).
Source voltage = I * 499 +Res.
Drain voltage = Supply - [I * Rd]
Gate voltage (assuming Id<+Idss) = Source voltage - Vgs.
If a bias is set at the gate, and that combined with Ir4 thus determines ALL the I values in those equations.
Do not set static DC bias current Id >Idss.
Vr4=4800mVdc.
Set R4=750r and Id = ~6mA (you can confirm this by measurement on the breadboard).
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Swordfishy, to me it seems like a mistake to bias the JFET through the feedback resistor R13, and could lead to instability. Maybe this isn't a valid concern, but I would much prefer a current source to bias the JFET like Lineup did in his circuit. Otherwise, it looks like a really nice design. And maybe my concern isn't valid but just seems like the amp is in chase the tail mode all the time.
John
John
Class A
and nice SPICE figures.
mikelm
swordfishy is back on the track:
JFET input - yes
MOSFET VAS- yes
Lateral out - yes
And I am happy, because this is the name of topic.
Now, if you get your DC-coupled Fetzilla to work
I will be even happier.
Because it is one original idea.
Actually noone has tested how stable DC.coupled really is.
Not with a real circuit.
In my spice there are no such things as temperatures and DC-drift.
It was AKSA-Hugh with his experience of amplifiers
that put a doubt to stability
and so we changed the original circuit.
Looks like you will make try. If it shows DC-offset problems
you can always make something else, like swordfishy.
and nice SPICE figures.
mikelm
swordfishy is back on the track:
JFET input - yes
MOSFET VAS- yes
Lateral out - yes
And I am happy, because this is the name of topic.
Now, if you get your DC-coupled Fetzilla to work
I will be even happier.
Because it is one original idea.
Actually noone has tested how stable DC.coupled really is.
Not with a real circuit.
In my spice there are no such things as temperatures and DC-drift.
It was AKSA-Hugh with his experience of amplifiers
that put a doubt to stability
and so we changed the original circuit.
Looks like you will make try. If it shows DC-offset problems
you can always make something else, like swordfishy.
Current source from negative to bias JFET is still my first choice.
It was AKSA-Hugh's idea with a variable volt ref to bias JFET gate.
Both ways work, but my choice, like yours, is a bias through CCS from negative supply.
I find it more estetic and it keeps the JFET sensitive GATE clean from eventual disturbance.
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