IRFP064 gets burnt

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xyz9915 said:
Do I need to connect resistor (1ohm) to the drains of the FET's for waveform analysis?
FETs are mounted in a large heat sink

What is your current? You'll probably need .01 or so ohm resistor if its 10-20A. Scope may not like the swinging drain.

You can insert it between the input and the center tap of transformer. You can try the source but you must keep in tight and small- added inductance can kill it.

Actually... A current tranformer is a better way to measure and you can measure right at the drain. Search digikey.com for 'current transformer'.
 
Pictures are still quite blurry and low resolution.

There seems to be a tall and long spike in Vds at MOSFET turn off, in other words, massive avalanch. This is enough to damage the MOSFET in the long term. The height of the spike depends on coupling between both primaries of the transformer(s), which may probably be improved a lot. This spike should not exceed 60V at full load. Search the forum on how to wind 12V push-pull SMPS transformers properly (toroid recommended). Slowing down gate turn-off may help too.

Gate waveforms seem taken from anywhere but from the gates since they don't reflect the plateau effect. Get used to look at the waveforms directly at MOSFET leads. Any PCB track will act as a small inductor at high enough frequencies, thus producing different waveforms at the other end.

The difference between both prototypes could be the way in which magnet wires are laid on the transformer(s) (critical!)
 
Slowing down gate turn-off may help too.

Since the attachment size is limited by 100K, thus I re-sized the picture to upload all waveforms in one file which result in less quality/blurry picture.

However, observing the traces 1,2,3 (left side, from top to bottom) it seems that there is no deadtime (although TL494 has maximum duty cycle around 45-48%). So, do you think that increasing deadtime may fix the problem? as the circuit works fine around 35% of full load.

In addition please help me how to slow down gate turn-off?
 
According to the pictures, dead time is approx 18% (or 9% + 9%) and it even seems enough for quasi-resonant operation, so it's ok.

The MOSFET get suddenly hot above a certain power level because the height of the turn-off spike increases with load and above 60V (actually 75V or so) avalanche arises and the energy stored in leakage inductance starts to be dissipated in the MOSFET.

Something that the pictures don't make clear is whether the spikes at both drains have similar amplitude or not. Dissimilar amplitudes are a sign of transformer saturation.

Gate charging and discharging speeds depend on gate resistors, but that part of your circuit is done wrong. BD139 and BD140 will get easily damaged that way, you can't use two independent emitter resistors, emitters should be joined and then connected to gate resistors (with optional diode for independent turn-on and turn-off speed setting).

Some disturbance in the control circuit caused by its own EMI could be causing the failure too.
 
Gate waveforms seem taken from anywhere but from the gates
According to the pictures, dead time is approx 18% (or 9% + 9%) and it even seems enough for quasi-resonant operation, so it's ok.

Eva! you are really an electronics freak (mentioned in Eva's profile). Your observation is correct, the gate waveforms are taken from driving circuitry but not from just gate of FET's.

However, tight coupling has fixed my problem & the circuits are functioning properly. Thanks for your expert guidance.

Now FET's are getting warm but not too much hot. However, the tall and long spike is still exist but its height is now reduced in a safer amplitude (around twice of applied voltage).
If I found any problem I will discuss in the forum, but I think that the matter is fixed.
Thanks again
 
As far as emitter resistors go, I wonder if the reverse biased b-e junction has similar properties to a zener diode. I have experienced that it does. Using suitable precautions has allowed me to build bench circuits that have not failed. I don't know about any further data than that.
 
Something that the pictures don't make clear is whether the spikes at both drains have similar amplitude or not. Dissimilar amplitudes are a sign of transformer saturation.

Hello EVA, although the problems is fixed.
but the spikes at both drains are not similar which indicate core saturation.
According to formula: Bac=(V*10000)/(4*Ae*F*N)
where f=36KHz, ae=1.73, N=2turns
therefore, 241 mT should be lower for the mentioned frequency. I changed the no. of turns from 2 to 3, or 4 & then also changed the frequency from 36KHz to 50KHz but spikes remain dissimilar.
since I want to build a high power smps (around 700w) so this will be the cause of mosfet's getting burnt.
So what do you suggest for balancing center-taped push pull primary winding? because it is much difficult to wind both ends similar even if wound bi-filar .

furthermore, if the half bridge circuit is used this will stop any DC component resulting core will not enter into the saturation. So please give your comments
 
Electrone said:
As far as emitter resistors go, I wonder if the reverse biased b-e junction has similar properties to a zener diode. I have experienced that it does. Using suitable precautions has allowed me to build bench circuits that have not failed. I don't know about any further data than that.

A reverse biased B-E junction is a very fragile zener. In small signal transistors you can't expect it to conduct more than a few dozen mA reliably. Damage may manifest as reduced gain and increased noise without causing the transistor to fail completely. Bigger transistors may handle more current reliably. B-E junctions should not be used to conduct that way unless current is well controlled.


xyz9915 said:


Hello EVA, although the problems is fixed.
but the spikes at both drains are not similar which indicate core saturation.

How dissimilar are them? A small mismatching at full power should be always expected. Balancing not only depends on winding resistance and leakage inductance, but also on PCB resistance matching, gate drive matching and pulse width mismatching in the control IC.
 
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