High Voltage Regulators (Maida or zener)

[trobbins]

Can you implement a time delay foldback in order to better manage a short-circuit condition. Ie. the pass current is reduced if a high voltage drop exists across the FET for a time exceeding allowable start-up conditions.

 

[tomchr]

I put a 3.3 Ohm resistor (R16) on the output of the regulator so that when the regulator is at its minimum voltage of 1.25V there will be 0.4A of current supplied.

Unfortunately, this makes your output impedance equal 3.3 ohm (give or take) as well. Would it work with R16 inside the feedback loop?

The circuit won't necessarily have to survive an indefinite short circuit. -- At least not in my application. But it would be nice if it could survive a few seconds of short circuit...

~Tom

 

[richwalters]

Is there any comments or concerns? I came up with the current limiting circuit myself so I am curious if anyone has seen this method before.

Yup......check for instability as drop out voltage approaches on load...this will make the error amp work near range extremities, also the threshold of current limit point.... both are key instability areas esp when PSU ripple is also thrown in. If RF instability is detected, back off immediately as RF generates masses of heat. Ferrite beads on the mosfet gates and drains solved my problems but I was never content with it. As SY mentions, finding a dv/dt bomb proof S/C is the achilles heel of the HV designs. The perfect home for those veteran WW2 junk box Carbon composition resistors. Nothing else can take it.

I tried this current limit pre reg method sometime ago and found my version unstable and snappy.....too much loop gain creating overcurrent on transient. When using an op amp as error, I found it performed better when the loop gain was really stopped down so that the no load/full load voltage performance drooped slightly. The transient response measurement is a good way to check overshoot, but be high voltage disciplined how on goes about doing it. X10-X100 Scope probe voltage ranges, isolation trannies and so on.
Be careful !

richy

 

[Rod Coleman]

Hey Guys,
Is there any comments or concerns? I came up with the current limiting circuit myself so I am curious if anyone has seen this method before. I hope the current limiting works. I should be able to test it tomorrow. Thanks everyone for your input. This is my first tube amp build and Maida regulator; so far everything seems to be going smooth.

Looks like good work!

You have actually improved the regulator a good deal, compared to the original Maida - by eliminating some of the clumsy poles in the original circuit, the dynamics will be neater. Also, the fixed resistor in the output means that the output impedance is more stable with frequency. Together, these changes may mean that the Regulator imposes itself less on the amplifier sound.

I am not convinced that the current limiter can be made (a) stable AND (b) quick enough to keep within the SOA of the FETs. Even 4 of them! If you do try to test the short-circuit performance, please remember that the FETs are likely to have slightly different Vgs for the same Id. If you add resistors in Each Source terminal, say 1 to 2.2 Ohms, the currents in each FET will be forced into equality. Otherwise, one FET will hog current, and die quickly. These resistors also help with stability of a multiple-FET source follower.

The soft-start is handy, but remember, it may not function during brief dropouts in the power.

 

[tomchr]

HV Regulator v. 2.0

Folks,

I just pulled the prototype board for this circuit out of the etch bath. I'm still planning on using a 0A3 for the reference voltage, but have left room on the board for a zener.

The only change compared to the circuit in Post #44 is that the series resistor to the reference has been extended to 3 x 47 kOhm.

~Tom

 

[jackinnj]

I've come across this scenario too..... repetive failures in PSU passes suddenly shut up with a large chip die.

Somewhat of a thread hijack,
BTW. I find it a somewhat disturbing trend that electronics inexperience gives way having to resort to spice and other simulation programs
<SNIP>
I'm not all against simulation programs but so much these days is worked adhock without a complete understanding of what's going on and this is bad.

I'm against folks trying to use Latin for the same types of reasons.

 

[desolationx]

I tested the current limiting on my regulator and it doesn't work THe LM317 will not survive turn on. For some reason when Q3 is attached as shown in the schematic, the LM317 fries on turn on. When I disconnect Q3, the regulator works great. Can the adjust pin on the 317 be put directly to ground and survive? Maybe a resistor in series with Q2 would help. The soft start circuit works great so I am puzzled as to why this is occuring. Any guesses?

How's your discrete regulator working Tom?

 

[Rod Coleman]

Sad to say, pulling the "GND" pin to GND will violate one of: Input-to-output voltage rating [40V for most versions], or output-to-GND. This may be a transient effect, but the chip will not be forgiving.

However, you have a husky power FET there already - why not connect Q3-drain to R4-D1{K} in order to throttle back the pass FET, in case of a short? You might have to increase R1 & R2 to keep fault-mode dissipation reasonable, but the 317 should remain unstressed throughout.

A small value cap from Q3g to GND could improve the stability of the trip mechanism; also consider a way of adding a little ac-hysteresis by diode-pulling Q1-b through a series RC network.

 

[tomchr]

Discrete Regulator Lab Measurements

The discrete regulator is coming to life. The output voltage depends slightly on the temperature of the error amp device, so on cold start, the output voltage is 472 V. As the regulator warms up, the output settles at 475 V. 0.63 % drift. I can live with that...

I decreased the compensation cap as the 10 nF I had in the schematic caused excessive ringing on load transients. Through experiments, I found 220 pF to be a good value. See updated schematic.

I ran a torture test of the regulator:
Start-up into no load.
Start-up into capacitive load.
Start-up into "short circuit" (cold light bulb).
Transient response.
Min. drop-out voltage measurement.
Ripple rejection.

The regulator passes with flying colors. Start-up into a 47 uF polypropylene cap (5 mOhm ESR) presents no problems at all. I even tried with the regulator at normal steady state operating temperature and high input voltage (120 VAC + 5 % = 126 VAC) on the transformer primary. No smoke...

Start-up into cold light bulbs throws the regulator into current limit. The current is limited to approx 120 mA. The voltage across the bulbs (four 25 W bulbs in series) is about 120 V. For this test the 47 uF cap was left in parallel with the bulbs by the way. I have not tested how long the regulator will survive this. I let it run for about 30 seconds to a minute. No sparks, smoke, or funky smells. The heat sink for the pass transistor was lukewarm after this...

The minimum drop-out voltage was found by reducing the input voltage to the point where 120 Hz ripple would show up on the output. The minimum drop-out is about 15 V. I.e. the input voltage must be 15 V higher than the output voltage for the regulator to maintain regulation.

The transient response is shown in attached o'scope pictures. Note that the vertical scale is 20 mV per division. Observant viewers will notice that the "fat" trace appears to be multiple traces overlaid. That is indeed the case. That phenomenon is caused by the ripple on the output of the regulator. This ripple measures 6 mVpp. The ripple on the input is 3 Vpp. Hence, the ripple rejection measures 54 dB. Not shabby... I should say, though, that my lab setup is currently a rats nest of wires. So once the layout gets tightened up I expect to have less 60/120 Hz pick-up in the circuit. Hence the ripple rejection measurement may improve.

The transient response is measured with a 25 % load step (45 mA to 60 mA). The response shows a tiny bit of overshoot followed by a fairly smooth settling. Of course, if the frequency of the load step is increased, the overshoot and undershoot will merge forming a waveform with higher amplitude. The final plots show the step response with a 20 kHz repeat rate for the step. When the load in suddenly increased, the output voltage drops until the regulator recovers. This takes about 1 us as shown in the zoomed plot. It's interesting to note that when the load is dropped, there isn't a similar increase in voltage. Funky... But we're counting millivolts here...

~Tom

 

[tomchr]

Hmmm.... The ripple rejection needs improvement. Even with only 6 mVpp on the output, I can hear the 120 Hz in the speakers when the regulator drives my 300B amp. Granted, it's not audible from the listening position, but still.... My speakers are 87 dB/W*m efficient. Not super efficient.

Aside from the hum, the amp sounds and measures good, though.

~Tom

 

[trobbins]

Hi Tom,

Did you have a reason for not putting D1 across Q1 g-s ?

Would it be worth putting a foldback on the base circuit on Q3?

Do you have the equipment to do small signal audio susceptibility and output impedance plots?

And were your step load plots done with any output load capacitance?

Ciao, Tim

 

[tomchr]

Did you have a reason for not putting D1 across Q1 g-s ?

In its current position, the zener protects the G-S of Q1 as well as Vce of Q3. Q3 is a 65 V device.

Would it be worth putting a foldback on the base circuit on Q3?

I'm not a fan of foldback as it's a circuit with more than one stable operating point. As I'm trying to protect Q1 from SOA over-stress during start-up, I need a fairly low current limit - say, 120 % of nominal output current. If the foldback triggers during normal operation, I'd be screwed...

Now, if the regulator was to be designed to survive an infinite dead short on the output, foldback would probably be a good option. Assuming, it could be designed to only trigger during over-current conditions while still keeping Q1 within its SOA limits.

Do you have the equipment to do small signal audio susceptibility and output impedance plots?

I have the gear, but not the test setup. For measurements of high voltages and supply output impedances, one doesn't just plug the gear in and push a couple of buttons. That said, I do sense some sort of electronic load project coming on... I'll have plots eventually.

And were your step load plots done with any output load capacitance?

Yes. I did them both with and without load cap but only showed the plots with load cap.

~Tom

 

[SY]

Is that really only 220pF for the speedup cap (C1)? If so, increasing it to 220nF will be helpful.

 

[tomchr]

Cascode anyone?

As usual the cascode comes to the rescue... 77 dB ripple attenuation at 60 Hz. I'll go fry some parts in the lab now.

I do admit that part of me wonders if a simple zener stack with a source follower would get the job done just as well. Granted, the output impedance would be Rds(on) throughout the entire audio range, but that's probably manageable. Especially as the Rds(on) for the STW12NK95 NMOS I'm using is specified to be about 0.66 ohm at 1 A (smaller for lower currents).

~Tom

 

[tomchr]

Is that really only 220pF for the speedup cap (C1)? If so, increasing it to 220nF will be helpful.

Yep. 220 pF. Increasing it to 220 nF causes excessive ringing (read instability). It's a zero-pole compensation. If the zero is moved too far down in frequency it won't do any good as the pole will have moved too far down as well. Hence, the phase is back to -180 deg (or below) at the 0 dB frequency.

~Tom

 

[Rod Coleman]

As usual the cascode comes to the rescue... 77 dB ripple attenuation at 60 Hz. I'll go fry some parts in the lab now.

I do admit that part of me wonders if a simple zener stack with a source follower would get the job done just as well. Granted, the output impedance would be Rds(on) throughout the entire audio range, but that's probably manageable. Especially as the Rds(on) for the STW12NK95 NMOS I'm using is specified to be about 0.66 ohm at 1 A (smaller for lower currents).

~Tom

If you have a Large-Area FET (one with high gm) this can work really well. The best part is that compensation is not necessary.

The high gm is needed, since the dynamic output impedance is 1/gm. THe gm will vary somewhat with current, so you get a little 'distortion', but the transient response will be more civilised without the feedback loop, in many cases. The listening tests may well show an improvement - I certainly preferred regulators with low open loop gain in my power amps.

Data sheet gm values are given at a large fraction of the drain current, so you get lower values at power-amp current levels - a 5 siemens FET may give 0.5 to 1.0S at 100mA, for example.

 

[Rod Coleman]

Is that really only 220pF for the speedup cap (C1)? If so, increasing it to 220nF will be helpful.

This is certainly not a speedup capacitor, so increasing the value to that level will cause havoc with the closed loop response.

The real function, as Tom has shown, is frequency compensation (placement of a zero to compensate an open loop pole). The shape of the output in response to a transient pulse will verify the choice of value.

 

[jackinnj]

Hmmm.... The ripple rejection needs improvement. Even with only 6 mVpp on the output, I can hear the 120 Hz in the speakers when the regulator drives my 300B amp. Granted, it's not audible from the listening position, but still.... My speakers are 87 dB/W*m efficient. Not super efficient.

Aside from the hum, the amp sounds and measures good, though.

~Tom

Is it in a chassis yet? Sometimes I will take a circuit, put it on a card table within a cookie tin in the middle of the room and use my SSM2019 battery powered amplifier to get away from all the 60Hz on the workbench. I also use shielded twisted pair for driving the regulators when measuring line rejection.

 

[SY]

This is certainly not a speedup capacitor

It sure looks like one to me. Take a look at Figure 6 in the His Master's Voice article. That's a reg with the same topology as this one, but using bipolars. That cap being large greatly reduces output noise and increases regulation. This is also discussed thoroughly in Morgan Jones VA3, pp 332-334.

 

[Rod Coleman]

It sure looks like one to me. Take a look at Figure 6 in the His Master's Voice article. That's a reg with the same topology as this one, but using bipolars. That cap being large greatly reduces output noise and increases regulation. This is also discussed thoroughly in Morgan Jones VA3, pp 332-334.

Speedup capacitor is a quite specific term for bypassing a base resistor in switching circuits. As Tom (and I) have explained, the C1 in this circuit is a frequency compensation capacitor in a feedback loop position. These are two entirely different things.

Increasing the value of the capacitor in that position might well reduce the noise level under static conditions, but a regulator for a power amplifier supply like this will suffer badly from such a change, because the transient response will yield a waveshape which is very distorted compared to the test waveform.

Tom has tuned the regulator correctly, by evaluating the transient response for different load steps, and picking the C1 value with the neatest response.