Somebody might recognize the schematic as similar to a design that is "on file" from a previous project, and adapt it to your requirements. It is more likely to be a completely original task. Some additional information can make it easier for the PWB layout person:
Is this a through-hole, SMT, or mixed design? 1 layer, 2 layers, or more? Limitations on trace size and clearance? Do you expect ground and/or power planes?
Do you prefer 1/8W, 1/4W, or 1/2W (or SMT equivalents) resistors?
Can you post a parts list with manufacturers' part numbers? Capacitors in particular are often available with a wide range of physical sizes and lead spacing for a given electrical rating.
Is there a sketch of desired physical size? Size & locations for mounting holes, I/O and power connections? Approximate component locations?
Without this information you are asking the PWB layout guy to do a lot of the design engineering, as well as the layout. With all of this information it would probably take me 4 hours to 8 hours to produce a basic 2-layer PWB layout - other people can probably do it in half that time. (It seems like I have to re-learn my PWB layout program every time I use it. Creating padstacks for new components, and harmonizing them with components already in my library, always seems to take a lot of time.)
Dale
Is this a through-hole, SMT, or mixed design? 1 layer, 2 layers, or more? Limitations on trace size and clearance? Do you expect ground and/or power planes?
Do you prefer 1/8W, 1/4W, or 1/2W (or SMT equivalents) resistors?
Can you post a parts list with manufacturers' part numbers? Capacitors in particular are often available with a wide range of physical sizes and lead spacing for a given electrical rating.
Is there a sketch of desired physical size? Size & locations for mounting holes, I/O and power connections? Approximate component locations?
Without this information you are asking the PWB layout guy to do a lot of the design engineering, as well as the layout. With all of this information it would probably take me 4 hours to 8 hours to produce a basic 2-layer PWB layout - other people can probably do it in half that time. (It seems like I have to re-learn my PWB layout program every time I use it. Creating padstacks for new components, and harmonizing them with components already in my library, always seems to take a lot of time.)
Dale
size ca. 13 by 13 cm double layer. MRS25 resistors 0,6w. All thru hole components. TO220 close to the edge for heatsinking. Spacing for film capacitors 15mm. Electrolytics 10mm dia.15mm.
mounting holes in corners. 2SC3381/2SA1349 double transistors. 2SC2240/2SA970 TO92 all Toshiba. Input/output at opposite ends of board. Groundtraces as big as possiple.
The files for the C3381/A1349 are too big. I have to shrink it before opload.
Thanks for the reply.
Poul
mounting holes in corners. 2SC3381/2SA1349 double transistors. 2SC2240/2SA970 TO92 all Toshiba. Input/output at opposite ends of board. Groundtraces as big as possiple.
The files for the C3381/A1349 are too big. I have to shrink it before opload.
Thanks for the reply.
Poul
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