I wish we could add such things into simulator.Well, it is one of those things that you have to abandon the simulator for. Simulator amps don't make much sound.The parasitics of the PCB/wiring is not so easy to model in a simulator.
As wire resistance and inductance.
You can model the parasitics. The inductances around the output and drive stages are particularly important, but 5-10nH per cm or thereabouts will soon let you know if you have a problem. Here's a link to a cascode related problem where the board pcb traces were modelled
http://hifisonix.com/wordpress/wp-c.../Cascode-Oscillation-in-Audio-Amplifiers1.pdf
http://hifisonix.com/wordpress/wp-c.../Cascode-Oscillation-in-Audio-Amplifiers1.pdf
http://www.ti.com/lit/an/snaa045/snaa045.pdf
Paragraph 7.1 page 17
"Dertermining gate resistor values"
Paragraph 7.1 page 17
"Dertermining gate resistor values"
I'm not sure if I understand you correctly, but I was agreeing with youWell, it is one of those things that you have to abandon the simulator for. Simulator amps don't make much sound.
I use the same technique in my currently playing MF80 amp. You're right that the sim doesn't show the oscillations, the parasitic L's are not modeled in the MOSFET models I was using. But on the bench, with my 200MHz scope I could make visible a 85MHz oscillation. In practice, a 47pF cap from drain to gate per FET was enough to have them shut up. N gate stoppers are 18 Ohm, P gate stoppers 15 Ohm. The stage is bloody fast.AndrewT, you have to look at it like this and in a sudden you'll get it being very easy:
Think of the power FET as an opamp with a non-inverting input (Gate) and an inverting output (Drain). Witih opamp circuits you often put a 10pF from the output to the antiphase input. This is similar in where you connect the transistor inverting output back to its input with a HF bypass. With this, forget that drains are connected to powerlines; it doesn't change the conceptual view of the drain being an inverting output to the gate.
Think of the power FET as an opamp with a non-inverting input (Gate) and an inverting output (Drain). Witih opamp circuits you often put a 10pF from the output to the antiphase input. This is similar in where you connect the transistor inverting output back to its input with a HF bypass. With this, forget that drains are connected to powerlines; it doesn't change the conceptual view of the drain being an inverting output to the gate.
P7 shows the oscillation topology.
P11 shows a Zobel from Gate to audio ground.
Where is the Zobel you refer to?
Base stopper for BJT
and gate stopper for JFET and MOS.
They all require different resistor values.
I wish we had a list for all types of Transistors.
For example typically for JFET 2SK170 and other.
I see for DN2540 is often used 100 Ohm.
In a circuit I have used 1 kOhm for small signal JFETs.
and gate stopper for JFET and MOS.
They all require different resistor values.
I wish we had a list for all types of Transistors.
For example typically for JFET 2SK170 and other.
I see for DN2540 is often used 100 Ohm.
In a circuit I have used 1 kOhm for small signal JFETs.
I think there shouldn't be such standard values. It can be for balancing the P-channel with N-channel, which i have never found 'attractive'. More important purpose is as part of the (stability) compensation, which means that it can be of any value depends on the overall design.
Latfets have limited transconductance so I will try not to have more than 100 Ohm there (often directly soldered to gate pin).
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