I have been looking at your revised circuit and started thinking about the time needed to shutdown T2 after an overcurrent trip. It appears that both the original and modified circuit would exhibit turn-off times in the 1.0 millisecond range (this is a back-off-the-envelope estimate). This is controlled by the time it takes to pulldown C6 via R6 in order to reduce the Vgs of T2 to the threshold voltage (or thereabouts).
I would like to suggest the following modification for your consideration:
Make R6 and R5 into a serial connection between C6 and T2's gate.
Move the Triac connection to the common node between R6 and R5.
Connect D1's cathode to T2's gate.
This would give a much faster shutdown for T2. R5 and R6 would provide a known bleed path for the output and input C's, respectively, during powerdown, after an overcurrent trip.
If you like the Triac's original load when R6=68 Ohms; then something like R6=R5=100 Ohms might be suitable. This preserves the original 200 Ohm resistance between C6 and T2's gate under normal Cap-Mult operation. I don't believe that the values for R5 or R6 are very critical and can be changed to suit a wide range of circuit prejudices.
Thanks again for sharing your circuit idea.
VSR
I would like to suggest the following modification for your consideration:
Make R6 and R5 into a serial connection between C6 and T2's gate.
Move the Triac connection to the common node between R6 and R5.
Connect D1's cathode to T2's gate.
This would give a much faster shutdown for T2. R5 and R6 would provide a known bleed path for the output and input C's, respectively, during powerdown, after an overcurrent trip.
If you like the Triac's original load when R6=68 Ohms; then something like R6=R5=100 Ohms might be suitable. This preserves the original 200 Ohm resistance between C6 and T2's gate under normal Cap-Mult operation. I don't believe that the values for R5 or R6 are very critical and can be changed to suit a wide range of circuit prejudices.
Thanks again for sharing your circuit idea.
VSR
I have a bit more thought about your proposed changes.
Let's assume a rail voltage of 16V (low by any standard) and a trip current of 4A. Further assume C7 to be 10,000uF, It will take something like 35ms to drain C7 by the load current (4A), if my quick-and-dirty calculation is not wrong. So much longer than 1ms. Hence the 1ms reaction time at the MOSFET gate is IMHO not critical.
I am not sure whether the proposal to drain C7 via D1 is really necessary or effective, as I would assume that the amp is still connected and drawing current. (I do not recall a discussion in this thread to incorporate a relay to separate the PSU from the amp.) The amp at trip current of 4A would probably be much faster at draining C7 than through R6, and putting D1 between Vout and gate of T1 would put unnecessarily strain on R6 and the triac ??
Regards,
Patrick
Let's assume a rail voltage of 16V (low by any standard) and a trip current of 4A. Further assume C7 to be 10,000uF, It will take something like 35ms to drain C7 by the load current (4A), if my quick-and-dirty calculation is not wrong. So much longer than 1ms. Hence the 1ms reaction time at the MOSFET gate is IMHO not critical.
I am not sure whether the proposal to drain C7 via D1 is really necessary or effective, as I would assume that the amp is still connected and drawing current. (I do not recall a discussion in this thread to incorporate a relay to separate the PSU from the amp.) The amp at trip current of 4A would probably be much faster at draining C7 than through R6, and putting D1 between Vout and gate of T1 would put unnecessarily strain on R6 and the triac ??
Regards,
Patrick
I have just checked the Vgs trace on tripping and the 'output protection diode' doesn't do anything! I have played around with the value of the capacitors and their discharge loads, and Vgs never exceeds the expected 4V or so. Still it isn't doing much harm either. I am not sure about the normal power down situation though.
The image above shows the power-up and trip characteristic. There are two significant time constants involved in the trip characteristic. These are the discharge of the output reservoir C7 and the discharging of C6 via R6 when the triac fires. With the circuit shown, the output reservoir C7 has an RC time constant of 11mS with a load current of 4A, whilst C6 and R6 have an RC time constant of 32mS. So the R6,C6 time-constant is the dominant one. Please note that on triggering, it is only C6 and it's discharge path R6 which count. The main reservoir capacitors remain fully charged and node R1, R2,C5 is discharged to ~ 50%
You can reduce the switch-off time by reducing the value of R6. The only caution is to make sure that the peak current through though triac does not exceed its rating. For a 20V supply, the gate voltage ~ 24V and the peak triac current will be 24/68 ~ 350mA which is fine for the device shown ( 4A rating). Reducing R 6 to 22 Ohms will give the same response as the output reservoir under a 4A load. Speeding things up further will require a reduction in the value of the output reservoir, C7.
I am not sure how fast it needs to be. Unlike a fuse, the circuit will not permit excessive currents. A quick-blow fuse will only blow quickly (mS) if the current is several time greater than it should be:
An externally hosted image should be here but it was not working when we last tested it.
The image above shows the power-up and trip characteristic. There are two significant time constants involved in the trip characteristic. These are the discharge of the output reservoir C7 and the discharging of C6 via R6 when the triac fires. With the circuit shown, the output reservoir C7 has an RC time constant of 11mS with a load current of 4A, whilst C6 and R6 have an RC time constant of 32mS. So the R6,C6 time-constant is the dominant one. Please note that on triggering, it is only C6 and it's discharge path R6 which count. The main reservoir capacitors remain fully charged and node R1, R2,C5 is discharged to ~ 50%
You can reduce the switch-off time by reducing the value of R6. The only caution is to make sure that the peak current through though triac does not exceed its rating. For a 20V supply, the gate voltage ~ 24V and the peak triac current will be 24/68 ~ 350mA which is fine for the device shown ( 4A rating). Reducing R 6 to 22 Ohms will give the same response as the output reservoir under a 4A load. Speeding things up further will require a reduction in the value of the output reservoir, C7.
I am not sure how fast it needs to be. Unlike a fuse, the circuit will not permit excessive currents. A quick-blow fuse will only blow quickly (mS) if the current is several time greater than it should be:
An externally hosted image should be here but it was not working when we last tested it.
I thought the axiom that a faster response to an overcurrent condition is preferred to a slower response would be logical and noncontroversial in the context of this thread.
In particular the suggestion I proposed in my previous post had no cost impact and required a minor rearrangement of previously included parts in Allan Newby's revised circuit as presently posted at the beginning of this thread. The proposal did not seem to change the dynamics of the circuit under normal operating conditions. It made the speed of response to an overcurrent trip dependent on the triac's Ton rather than the time to remove energy from a filter cap. Thus, instead of responding in a 1.0 millisecond time frame it would respond in a 10 microsecond time frame.
If the point is the current response time is adequate. Then this presupposes that an exhaustive failure analysis for the current load (amplifier) has been accomplished. It further presupposes that the analysis is some how definitive for the different loads (amplifiers) that other potential user's of Allan's idea might choose to implement. Even with such an analysis; I still believe that faster is preferable, especially if it costs the same as slower.
Thank you for your indulgence,
VSR
In particular the suggestion I proposed in my previous post had no cost impact and required a minor rearrangement of previously included parts in Allan Newby's revised circuit as presently posted at the beginning of this thread. The proposal did not seem to change the dynamics of the circuit under normal operating conditions. It made the speed of response to an overcurrent trip dependent on the triac's Ton rather than the time to remove energy from a filter cap. Thus, instead of responding in a 1.0 millisecond time frame it would respond in a 10 microsecond time frame.
If the point is the current response time is adequate. Then this presupposes that an exhaustive failure analysis for the current load (amplifier) has been accomplished. It further presupposes that the analysis is some how definitive for the different loads (amplifiers) that other potential user's of Allan's idea might choose to implement. Even with such an analysis; I still believe that faster is preferable, especially if it costs the same as slower.
Thank you for your indulgence,
VSR
Is this shrerelec's variation?
If so, the triac does indeed pull the gate down in microseconds. The 2200µF output reservoir with will still take 11mS or thereabouts to discharge, but nevertheless the mod suggested by sherelec is a welcome improvement. Faster has got to be better.
An externally hosted image should be here but it was not working when we last tested it.
If so, the triac does indeed pull the gate down in microseconds. The 2200µF output reservoir with will still take 11mS or thereabouts to discharge, but nevertheless the mod suggested by sherelec is a welcome improvement. Faster has got to be better.
> Is this shrerelec's variation?
I don't think so.
As it is shown, when the triac is on, it will also drain C7 through D1 without any current limiting resistor, and is likely to damage the triac.
I think you want to put R5 where you now have R6 (i.e. between C6+ and T2 gate) and R6 between T2 gate and Triac. Cathode of D1 also goes to T2 gate. That way, C7 is discharged both through the amp and D1-R6-Triac-Ground.
But I personally would remove D1 altogether.
I agree that it is an improvement, and I would also implement it as such. Especially when the time constant of C6-R6 is till rather long.
Patrick
I don't think so.
As it is shown, when the triac is on, it will also drain C7 through D1 without any current limiting resistor, and is likely to damage the triac.
I think you want to put R5 where you now have R6 (i.e. between C6+ and T2 gate) and R6 between T2 gate and Triac. Cathode of D1 also goes to T2 gate. That way, C7 is discharged both through the amp and D1-R6-Triac-Ground.
But I personally would remove D1 altogether.
I agree that it is an improvement, and I would also implement it as such. Especially when the time constant of C6-R6 is till rather long.
Patrick
To Allen Newby,
Sort of, the schematic you have posted is a good representation of my thinking, but D1 needs to be connected to T2's gate.
There are two additional tweaks that should help this circuit weather electronic mishap:
Make D1 a 10-15V 1W Zener (leave the anode/cathode orientation the same as the current 1N4004). This will further protect T2 against a hard short across C7 by insuring that the Vgs does not exceed +20V.
Add a resistor in series with T1's base so that a hard short across the input C's will not allow the base current to exceed 0.1 times the max collector current rating for T1, under reverse breakdown of T1's B/E junction. In this scenario the body diode will force the current sense resistor to be the main ballast impedance between the output C's and the input C's. I do not believe the triac has a way to respond to this condition, nor does it matter; as the body diode will be forced into conduction independent of T2's gate drive.
Finally I have misspelled your name (twice!) in my previous post. I beg your pardon.
VSR
Sort of, the schematic you have posted is a good representation of my thinking, but D1 needs to be connected to T2's gate.
There are two additional tweaks that should help this circuit weather electronic mishap:
Make D1 a 10-15V 1W Zener (leave the anode/cathode orientation the same as the current 1N4004). This will further protect T2 against a hard short across C7 by insuring that the Vgs does not exceed +20V.
Add a resistor in series with T1's base so that a hard short across the input C's will not allow the base current to exceed 0.1 times the max collector current rating for T1, under reverse breakdown of T1's B/E junction. In this scenario the body diode will force the current sense resistor to be the main ballast impedance between the output C's and the input C's. I do not believe the triac has a way to respond to this condition, nor does it matter; as the body diode will be forced into conduction independent of T2's gate drive.
Finally I have misspelled your name (twice!) in my previous post. I beg your pardon.
VSR
Thanks to the various contributions, I think we now have a final version which although aimed at A class amps, could be used in almost any application?
I have updated the write ups:
psu.pdf
PSU.html
The image shown at the start of this thread has also been updated.
If I get time, I will alter and post the pcb artwork.
I have updated the write ups:
psu.pdf
PSU.html
The image shown at the start of this thread has also been updated.
If I get time, I will alter and post the pcb artwork.
> If the output were a dead short, it is possible that the voltage on the output reservoir C7 would collapse more quickly than the voltage on C6. This would result in a brief, positive Vgs spike that could be damaging. Hence the orientation shown.
Very true. However, ...
If not a dead short (since the Triac will now act real fast in microseconds and directly at the gate with C6 somewhat buffered through R6), then the MOSFET will see a negative spike. Perhaps two ZDs of the same voltage back to back ? Then both case covered.
Patrick
Very true. However, ...
If not a dead short (since the Triac will now act real fast in microseconds and directly at the gate with C6 somewhat buffered through R6), then the MOSFET will see a negative spike. Perhaps two ZDs of the same voltage back to back ? Then both case covered.
Patrick
Too Zener or Two Zener?
Patrick,
The ZD1 orientation provides a clamp at ~10V and ~-0.6V for Vgs on T2. This would seem to be all that is needed. Expanding the negative window with a back to back Zener does not seem to buy anything useful, and more parts is not a benefit. The use of a single Zener provides the negative clamp of the original D1 while adding a specifiable positive clamp, all in one low cost component.
If you need back to back Zener operation (with symetrical breakdown), then you might also consider using a bidirectional transorb (semiconductor transient suppressor, not a MOV). These are cheap, well specified, and rugged compared to a regular Zener of similar voltage and size.
Finally unless you are considering operating T2 in the "Ohmic" region (Rds limited) then there is no benefit in exceeding 7 or 8V of positive Vgs bias for this type of MOSFET. In fact, if you need this much bias in a steady-state voltage controlled mode; then you are going to have serious trouble keeping the package cool for long term reliability. You need to consider using a larger die and larger pkg in order to get back to a 4 or 5V normal Vgs. Remember these devices were designed for switching. Thus, high current, high Vgs operation was considered for Rds limited operation with only brief switching transients outside this region.
I hope this is useful.
VSR
Patrick,
The ZD1 orientation provides a clamp at ~10V and ~-0.6V for Vgs on T2. This would seem to be all that is needed. Expanding the negative window with a back to back Zener does not seem to buy anything useful, and more parts is not a benefit. The use of a single Zener provides the negative clamp of the original D1 while adding a specifiable positive clamp, all in one low cost component.
If you need back to back Zener operation (with symetrical breakdown), then you might also consider using a bidirectional transorb (semiconductor transient suppressor, not a MOV). These are cheap, well specified, and rugged compared to a regular Zener of similar voltage and size.
Finally unless you are considering operating T2 in the "Ohmic" region (Rds limited) then there is no benefit in exceeding 7 or 8V of positive Vgs bias for this type of MOSFET. In fact, if you need this much bias in a steady-state voltage controlled mode; then you are going to have serious trouble keeping the package cool for long term reliability. You need to consider using a larger die and larger pkg in order to get back to a 4 or 5V normal Vgs. Remember these devices were designed for switching. Thus, high current, high Vgs operation was considered for Rds limited operation with only brief switching transients outside this region.
I hope this is useful.
VSR
Patrick..
I think sherelec is right, the zener diode acts like a conventional diode when forward biased and will also protect the gate from positive spikes when the triac fires.
Russ...
The overcurrent protection would be good, especially when setting up your experimental amp. The mains ripple rejection of the PSU is pretty good, better than -60dB, or a few mV. However, the output impedance is equal to the inverse transconductance and is load current dependant: ~50 mΩ for a 3A load current. Because of this series resistance, a component of the audio signal will be super-imposed on the output of the Power Supply. At full power, the supply voltage modulation will be around 100mV, a fair bit more than the mains ripple.
Fortunately, with A class amps, the AC load current varies linearly with the audio signal and the full wave audio signal super-imposed on the PSU output has no effect on amplifier distortion.
With pure class B, the supply voltage modulation on each rail is in the form of a half wave audio signal component. With your A-B amp, the supply voltage modulation ought to be a clipped full wave signal.
If your design includes differential input stages, current source/sinks instead of resistive loads, symmetrical configuaration etc then you are likely to have a pretty good PSRR figure.
If at full 8A load, you have say 200mV of PSU modulation and your amp has a PSRR of -60dB, you will see 0.2mV at the amplifier output at full volume. Barely audible.
I think sherelec is right, the zener diode acts like a conventional diode when forward biased and will also protect the gate from positive spikes when the triac fires.
Russ...
The overcurrent protection would be good, especially when setting up your experimental amp. The mains ripple rejection of the PSU is pretty good, better than -60dB, or a few mV. However, the output impedance is equal to the inverse transconductance and is load current dependant: ~50 mΩ for a 3A load current. Because of this series resistance, a component of the audio signal will be super-imposed on the output of the Power Supply. At full power, the supply voltage modulation will be around 100mV, a fair bit more than the mains ripple.
Fortunately, with A class amps, the AC load current varies linearly with the audio signal and the full wave audio signal super-imposed on the PSU output has no effect on amplifier distortion.
With pure class B, the supply voltage modulation on each rail is in the form of a half wave audio signal component. With your A-B amp, the supply voltage modulation ought to be a clipped full wave signal.
If your design includes differential input stages, current source/sinks instead of resistive loads, symmetrical configuaration etc then you are likely to have a pretty good PSRR figure.
If at full 8A load, you have say 200mV of PSU modulation and your amp has a PSRR of -60dB, you will see 0.2mV at the amplifier output at full volume. Barely audible.
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