F5 with P3 under analysis - why it works
I way mystified about why the P3 adjustment worked so well and undertook a serious mathematical analysis of the F5 dual feedback loops.
The bottom line is that when P3 is adjusted to minimize 2nd harmonic distortion it also guarantees equal AC currents in both circuits, which important maximize output wattage before transitioning into class-AB. This result is independent of the matching of JFETs and MOSFETs.
I have a formal mathematical analysis in Maxima that describes this that I am willing to make available.
I way mystified about why the P3 adjustment worked so well and undertook a serious mathematical analysis of the F5 dual feedback loops.
The bottom line is that when P3 is adjusted to minimize 2nd harmonic distortion it also guarantees equal AC currents in both circuits, which important maximize output wattage before transitioning into class-AB. This result is independent of the matching of JFETs and MOSFETs.
I have a formal mathematical analysis in Maxima that describes this that I am willing to make available.
I am mystified now . . . we try to maximize 2nd harmonics of the right phase, don't we? (see my avatar . . that shows a tube output).
Yes of course you can make it into a full differential/symmetric AC current flow, but that operating has been avoided by many with all kinds of tricks. They often are about misaligning the two FETS of BJT on the input along the operating curve, just a few mV's sometimes. And that brings up the different character.
The DC is balanced in Papa's smart setup with the current balancing pots P1 P2 on the drains (otherwise, like in Hiraga's setup for example) the balancing pot P3 also balances the DC operating point.
Can you also find that point in the math, that would be cool.
albert
Yes, roughly my solution does the following.
Each JFET+MOSFET chain is approximated by a 2nd order polynomial, which is essentially the same as the MOSFET equation:
I(Vgs)=k*(Vgs-Vt)^2.
Note that k is related to transconductance by:
k = Gm^2/(4*Ibias)
To achieve the idle bias current Ibias (and zero output offset voltage), each Vt is chosen as:
Vt=-sqrt(Ibias/k).
This is equivalent to the adjustment of the pots P1 and P2.
The math for modelling the pair of interacting feedback loops gets complicated, but essentially it is of the form:
Vout = (k1*((1-a1*Gain)*Vin-Vt1)^2 - k2*(-(1-a2*Gain)*Vin-Vt2)^2) * Rload
where a1 and a2 are the attenuation factors of the feedback networks involving R1, R5, R7, P3 for the upper amp chain, and R2, R6, R8, and P3 for the lower amp chain.
Gain = ((1-a2*Gain)*Gm2 + (1-a1*Gain)*Gm1) * Rload
2nd-distortion = ((1-a1*Gain)^2*k1 - (1-a2*Gain)^2*k2) * Rload
It is easy to solve the above equations for a1 and a2 to achieve the desired closed-loop gain and zero 2nd order distortion to get:
a1=1/Gain-1/(2*Gm1*Rload)
a2=1/Gain-1/(2*Gm2*Rload)
I hope this helps understand what I am doing.
Ok so I used some wires and clipped in a p3 on one channel and hooked up my amp in arta. I was able to use the fft display to see how p3 affects the distortion of the amp. I also see that as f2 goes down, f3 raises up. I would think that having a distortion spectrum with lower odd order harmonics might be more pleasing to the ear as opposed to just having the lowest measurable distortion. Has anyone spent time trying tis with the f5?
A more noob question I have. Is there any mechinism by which you can cancel 3rd or odd order harmonics in a circuit?
A more noob question I have. Is there any mechinism by which you can cancel 3rd or odd order harmonics in a circuit?
lhquam - Absolutely clear!
It shows the working of the two halves.
In fact this could be produced as a spreadsheet where we fill in the specs of our four devices - that brings us k.
By the way - in my implementation I did most work of selecting the feedback pairs (in your formula - a1 and a2 are the attenuation factors of the feedback networks) because I thought that with misalignment there would 'hogging' of the output. In fact, when I added caps across the feedbacks I saw wild oscillation (damped) could occur at very high frequencies if the two parts were out of synch.
With your formulas you show the important element of including the P1//R3 and P2//R4 in our thinking, not just P3.
How about the third harmonic?
Because we actually like to reduce that .. . and not to the expense of the second.
I'll look for some old pictures to illustrate what I mean.
It shows the working of the two halves.
In fact this could be produced as a spreadsheet where we fill in the specs of our four devices - that brings us k.
By the way - in my implementation I did most work of selecting the feedback pairs (in your formula - a1 and a2 are the attenuation factors of the feedback networks) because I thought that with misalignment there would 'hogging' of the output. In fact, when I added caps across the feedbacks I saw wild oscillation (damped) could occur at very high frequencies if the two parts were out of synch.
With your formulas you show the important element of including the P1//R3 and P2//R4 in our thinking, not just P3.
How about the third harmonic?
Because we actually like to reduce that .. . and not to the expense of the second.
I'll look for some old pictures to illustrate what I mean.
Adding capacitance from the JFET source to ground is exactly the wrong thing to do. It will boast the high frequency gain and leasd to oscillation. To lower high frequency gain, add capacitance across the feedback resistors R5-R8.
The third harmonic is in-phase with signal and cannot be cancelled by a a push-pull pair. If a 3rd order term were included in the two amp chain equations, it would show up as an additive rather than subtractive term in the output. I conjecture that the odd harmonics would look something like:
((1-a2*Gain)*XXX1 + (1-a1*Gain)*XXX2)*Rload
where XXXi has units of Amp/Volt^n, where n is the harmonic number.
What are the major contributors to distortion in the f5? If you remove current limiting and the thermistors, there are very few parts to this amp. It would seem to me that component selection would be critical at every point of this amplifier.
Are there ways to combat the largest contributors to distortion in this amp?
Are there ways to combat the largest contributors to distortion in this amp?
The intrinsic square-law characteristics of the JFETs and MOSFETs cause nearly all of the distortions. Proper adjustment of P3 can reduce even order distortions to nearly zero. Increasing the bias currents helps, but increases idle power dissipation. Nothing much can be done to reduce odd order distortions other than increasing the amount of negative feedback, at the cost of increasing distortions at higher orders.
So if we make the solving a bit more complicated, we could say - instead of nulling second harmonics al together - for example set that at 10 dB higher than 3rd harmonics (which is a given and can be calculated, given the measures characteristics of the devices).
The picture below shows what I think happens, this picture is from a differential pair by the way (Héphaïstos, in L'Audiophile 2/1988).
With P3 we also move the operating point a bit up or down, and are content with the trifle of added second harmonics (as long as they are in phase, being natural).
albert
by the way, I did try to lower high frequency gain for a high roll-off, by adding capacitance across the feedback resistors R5-R8, even 2 nF matched to about 2% was not good enough and gave damped ringing (way above 100kHz), so at the end I left the bandwidth all open myself, and that sounded best.
Yes, it is now obvious what is going on here. The feedback caps c1,c2 would have to be precisely adjusted. Without the feedback caps, the
attenuation factors are computed as follows:
Let the attenuation network be from the resistor divider Rg, Rf, where Rg' connects to ground, Rf to the amplifier, and the common node to the JFET source. Rg' is R1||z*P3. The attenuation factor is:
a = Rg' / (Rf + Rg')
With a capacitor C across Rf, we get
a(f) = Rg' / (Rg' + Rf || -j/(2*pi*f*C))
It might be impossible to maintain balance across all frequencies.
It the objective is to roll off the frequency response, rather than prevent oscillation, Nelson has suggested a capacitor from the JFET gate to ground.
